Info
Info
News Article

System On A Chip

News
Meeting system design challenges of physics and environment
As integrated circuit technology pushes onwards through 32nm, 22nm and beyond, system chip designers will need to come up with solutions for the inherent variability of near-atomic level structures. Dr Mike Cooke reports on possible ways forward presented at Future Horizons’ International System and System-on-Chip(SoC) Forum at the end of 2007.

Out of necessity, chip designers are becoming increasingly aware of the physical limitations of silicon CMOS devices in addition to the system complexity that they have been dealing with for some time. Also, the emphasis of recent times on wireless networking and communication of consumer devices has raised the profile of the analogue technology needed to receive, transmit, encode and decode radio signals. This means that a conference such as Future Horizons' International System and SoC Forum in Prague, Czech Republic, has to deal with what semiconductors can and will be able to deliver in both areas.


As Scott McGregor, CEO of Broadcom, commented, “You can only divide atom numbers by two only so many times.” McGregor believes that as the end of the useful life of silicon electronics approaches fabless companies are going to increasingly need to be involved in understanding and developing process technology. Going beyond silicon, says McGregor, “is a problem our children will have to face.”


""


Design on a shaky platform
Rudy Lauwereins, vice-president for Nomadic Embedded Systems at the IMEC development centre in Europe talked of the problems of system design with an inherently unreliable process technology. As transistors enter the atomic regime, changing just one atom in a structure can give devices that run too hot or too slow (Fig 1), leading to transistors with an expected lifetime of less than a year. If 22nm, as is likely, performs worse in this respect than 32nm node technology, there may be no drive to progress further to new silicon technology levels.


To deal with this, IMEC is developing design and modelling techniques that can handle process variations. One proposed capability is to build in circuit ‘monitors' that detect circuit performance and ‘knobs' that adjust particular chips to optimum operation. It is expected that as a circuit ages its optimum operating point will change (Fig 2). This feature is already seen today and will no doubt increase as technology advances to smaller devices.


""


Another direction in which IMEC is working to increase capability and reduce footprints is in three dimensional stacked devices. This allows integration of heterogeneous technologies, resolves interconnect bottlenecks and gives shorter leads, increases function with extra layers, and creates more modular and scalable designs. Lauwereins suggests that ‘sleek form factor' 1mm3 stacks could replace 50mm2 of silicon on a circuit board (Fig 3). IMEC is working on providing 3D design capabilities, at the moment on adding through-silicon-via (TSV) connections to design tools. Presently, TSVs perform worse than traditional connections, but they have the capability to eventually give much better performance.


""


Package level integration
Jon Lanson, European general manager of Amkor, also considered opportunities for new multi function packaging configurations. Amkor is a supplier of outsourced IC package and assembly. Outsourced assembly and test accounts for an increasing fraction of the total market and is expected to reach 50% in 2010.


Not all applications are best served by single chip solutions, says Lanson. Package level integration can be an effective alternative, using 3D stacking and flip-chip technologies. New wafer-level chip-scale and advanced lead frames can be used to shrink component sizes and increase performance.


Today, some 75% of mobile phones contain a camera. Lanson expects the tendency to integrate non phone functions to move on to mobile TV and GPS positioning capabilities. Mobile TV use may not be just, or even predominantly traditional programming, the platform could be ideal for sharing the low resolution clips out on the internet on YouTube and similar sites.


To achieve the near-PC performance needed in such mobile TV-enabled phones, Lanson expects that a broad set of new product and process packaging capabilities will be needed, including package-on-package (PoP), stacked die chip scale (S-CSP), wafer level, through silicon vias (TSV) and CMOS image sensor (CiS). Currently, flip-chip packaging technology is ‘boutique', but Lanson expects it to become an enabler of low-cost high volume products such as modules containing baseband processing and front end radio frequency components. With increasing gold prices, wafer- evel packaging and flip chip become more attractive low-cost alternatives to wirebonding.


As opposed to single-chip systems, systems-in-package can integrate a wide range of technologies that are not standard CMOS, surface-acoustic wave (SAW) devices, power amplifier modules built from III-V semiconductors rather than silicon, shielding, micro-electro-mechanical systems (MEMS), etc.


Lanson reports that Amkor has shipped some billion modules, radios, baseband and companion circuitry for mobile devices and sensors for biometric and mass storage applications. There has been a great expansion in the past 12-18 months so that where the technology was ‘coming' a couple of years ago it is ‘more than just coming' now.


Amkor is also working to provide shielding of systems in noisy RF environments. One method is to embed a stamped box of C194 copper alloy around the device in a package, adding almost a millimetre in the lateral directions. Seeking to crush dimensions further, Amkor is working on conformal shielding and is now finalising the process after alpha customer sampling.


Reaggregation needed
Kevin Meyer, vice president at Singapore's Chartered Semiconductor foundry, spoke of the increasing need for collaboration for semiconductor production technology progress. The first major ‘speed bump' to the traditional pace of development (‘Moore's Law') came at 0.13µm (~2001) and more can be expected going forward. Every new shrink will need high yields to make such a technology shift cost effective. Otherwise development could cost more than making do with parts from the older, larger technologies.


Meyer points out that while many semiconductor businesses have gone through a lengthy economic process of deaggregation, in which foundries like Chartered have played a prominent part, the new technology tendencies require rather some form of ‘reaggregation'.


One aspect supporting reaggregation for Chartered is its development with others (IBM and Samsung) of a common technology platform. This has enabled Chartered to move from significantly trailing to now meeting the International Technology Roadmap for Semiconductors (ITRS) schedule (Fig 4). Freescale, STMicroelectronics and Infineon also work with these companies in a ‘Joint Development Alliance' on process and design issues. The platform plugs into an extensive design ecosystem. Amkor also works with the IBM alliance.


Such collaboration is vital to Chartered's planned development. Meyer admitted Chartered would be unable to implement new high-k insulator and metal electrode gate stacks without such joint work. More non scaling transistor innovations are on the horizon (Fig 5), ultra thin body silicon on insulator, double gate, FinFETs, etc.


Two main camps for such work seem to be developing (there have also been some previous permutations), that around Chartered, IBM and Samsung, and, attempts (not very successful, according to Meyer) by the Japanese to work together. Outside these camps come the two main Taiwan foundries, TSMC and UMC, and Intel, with its non foundry compatible process.


""


On-chip analogue/digital designs
According to John O'Brien, CEO of Silicon & Software Systems (S3), system-on-chip economics are driving analogue/digital (A/D) interface on-chip in pure CMOS technology. O'Brien estimates that 75% of systems-on-chip have some analogue component. Since the transistors have ‘zero' marginal cost, it is crucial that analogue intellectual property (IP) circuit designs are proven to work in silicon. Gartner Dataquest estimates that the value of the analogue IP market is growing at 40% per year, while the expected growth of semiconductor revenues in 2010 (US$2.7 billion) represents a 14% compound annual growth rate over 2005's US$1.4 billion. Among the applications needing analogue are wireless networking, digital TV/radio, video and A/D, D/A encoders.


Analogue/digital or D/A conversion is often the limiting factor for the performance of a SoC. Analogue IP companies need to be involved early in the development of new semiconductor processes at foundries and integrated device manufacturers. Among the reasons for this is the need to improve circuits so that they can run at lower power. These improvements generally involve tweaks in circuit and process technology. The need for tweaks and other customisations limit the reusability of analogue IP. “It is not off-the-shelf technology”, says O'Brien. S3 has already developed silicon proven analogue IP at 65nm.


Broadcom's McGregor reports that his company works to defined processes, taking variability into account. For example, radio chips must contain circuitry to self calibrate. Broadcom's analogue circuits are targeted at CMOS, not BiCMOS, processes. Indeed, Broadcom was founded on a research thesis aiming to produce RF circuits on standard CMOS.


McGregor sees little advantage deriving from owning semiconductor manufacturing facilities. He maintains that people tell themselves things that are not true about having fabs, for example, about costs. Indeed, he told himself these things when he was running Philips Semiconductors. Those who say that owning production capability enables process tweaking are making excuses. “There are always other ways on a standard process,” he says. “I wouldn't go back,” says McGregor looking back on his experiences at Philips. He is now content to leave process technology to the specialists.


Radio down to last 25m
John Scarisbrick, Cambridge Silicon Radio's CEO until the end of 2007, described the problems of speeding the ‘last 25 metres' of the home network. The challenges involve wired systems from the ‘plain old telephone service' (POTS) to fibre-to-the-home (FTTH), wireless systems to third generation and beyond, and satellite and terrestrial video/radio signals. These involve analogue, digital, wireless and optical technologies.


Among those attempting to meet these needs is Cambridge Silicon Radio (CSR) that has designed radio systems in pure CMOS technology. At the beginning, CSR was told that what it was doing was “stupid, impossible or both”, but CSR did it. Its single chip RF/analogue/digital chip solution now has some competition but in comparison one competitor chip needs 20% more area for the radio section, 50% more for inductors and is overall 24% larger. The company has seen significant success in the Bluetooth market.


For RF and analogue rich components the traditional lithography dogmatism of pushing the dimensions down to the smallest limit is not necessarily the right solution, says Scarisbrick. The process level instead should be chosen to provide the correct performance and cost balances.


""


Creating analogue reuse families
John Heugle, CEO of austriamicrosystems, described how his company had moved production from application specific integrated circuits (ASIC) to standard products. While many in the industry think of austriamicrosystems as being a ‘foundry', some 85% of the company's business is in producing its own products, with the emphasis on analogue and analogue enablement of digital designs. In-house production takes place in Austria where the company has a 200mm wafer fab with a 0.35µm analogue CMOS base process (identical with that of TSMC) and high voltage, silicon germanium and embedded Flash/EEPROM capabilities. Austiamicrosystems also uses TSMC (analogue and digital CMOS) and Infineon (a process licensee of the company's high voltage process). From 2009, IBM will also supply high voltage parts as another process licensee. Heugle further boasts that austriamicrosystems is the only semiconductor company that owns a castle (Fig 6)!


Austriamicrosystems' products include devices for power and lighting management, mobile entertainment, medical imaging, magnetic rotary encoders, and next generation automotive high speed data bus systems. The medical imaging section accounts for some 38% of the company's revenue. Here, sensitivity is the key requirement. Austriamicrosystem still champions the use of BiCMOS for this application since its improved signal-to-noise capabilities enable simplified components and lower dose rates for damaging radiation such as x-ray.


Austriamicrosystems develops intellectual property and product platforms first with a ‘lead product' for one of its important customers, but then aims to maximise the reuse of IPdeveloped into a wide range of derivatives.


In this way, the company can reduce development costs by some 30% and be in the market place 25-30% quicker. The company has reuse thresholds to guide it in giving approval for development of new products. A derivative component will ideally contain more than 70% reuse of previous work. IP reuse also allows reliability characteristic tracing of particular designs. Heugle criticised companies that labelled everything a ‘platform', “You can't have everything as a ‘platform'. If you do, you're doing something wrong.”


Technology to meet environment challenges created by technology
Rich Goldman, vice-president of Strategic Market Development at Synopsys, sees opportunities for complex system-on-chip development to meet the need to reduce power consumption and therefore emissions of carbon dioxide and other greenhouse gases.


“Engineers accept the scientific evidence,” says Goldman. It is estimated that at current rates of depletion, the polar ice cap will be gone by 2030. Increasing world population, life expectancy, energy use, and carbon emissions are expected and all interconnected. A US$3.50/gallon gas prices (considered extortionate in the USA) have shocked the US population into thinking about energy conservation.


Although much of the recent spotlight has fallen on increased levels of air travel as a factor in increasing CO2 levels, some see the increased use of computers and related equipment as having as big, if not a bigger, impact. Semiconductor sales have been given successive boosts from the dispersion of computer (1980s), connectivity (1990-2000s) and now consumer electronic equipment. A new factor is increasing globalisation that is opening up virgin consumer sectors in the fast developing regions such as China (6x GNP in period 1990-2005) and India (3x GNP).


Although the world's 2.3 billion mobile phones are estimated to draw about 100MW/day, equivalent to two large wind farms, PC usage is far more serious. 1 billion computers in an on-state for about 9 hours draw 95GW/day uses the output from 114 large coal-fired power stations. This difference means that more opportunity for lowering emissions comes from focusing on wired equipment such as PCs for power savings.


Goldman pointed to estimates that of the US$250 billion spent globally each year powering electronic devices about 85% of the energy is simply wasted in idling standby states.


This estimate is based on studies in France (7% wasted in standby), and in the Netherlands, Australia and Japan where up to 13% wastage was found.


Among the main challenges for power management is the increase in static power drain compared with useful ‘dynamic' power at advanced process geometries.


The recent moves to replace silicon dioxide with high-k have been among the process technology responses to increasingly thin, leaky gate insulators. With the increase in power waste, the trend of power density increase from the Pentium 4 to those of nuclear reactors, rocket nozzles or even the surface of the Sun changed the emphasis at Intel from increasing clock speeds to multiple cores.


Goldman pointed out one irony of the increasing ‘function' levels in mobile phones, less functionality in terms of talk time. A 2004 2.5G phone has 320 minutes of talk time, while a 2006 3G device has 130 minutes (or just 70 minutes of video talk). Goldman reported his personal response, go back to the old phone (with consequent reductions in phone and chip sales).


Legislative and consumer responses have already been made in the area of environment concerns. A prime target is replacing traditional light bulbs that put out about 10% of the energy consumed as light with more efficient compact fluorescent lamps (CFLs) and light emitting diodes (LEDs). Traffic lights are being gradually replaced with LEDs.


New technology initiatives should include intelligent power supplies, battery powered cars, and, using electronic networks rather than travelling. Intelligent power control could save 70% of the energy presently used to power washing machines, Goldman estimates.


To deal with the standby power issue, the UK government has stipulated that digital TV set-top boxes should be reprogrammed to switch off overnight. This move is expected to reduce UK electricity bills by US$15 million and CO2 emissions by 32kilotonnes.


Synopsys has been developing power-efficient design techniques for about 10 years, but has only recently seen significant interest from customers. “In the first 5-7 years there was no market traction,” admits Goldman. Such Synopsys techniques were used in Toshiba's 90nm media processor system on chip that boasted 40% power reduction.


""



AngelTech Live III: Join us on 12 April 2021!

AngelTech Live III will be broadcast on 12 April 2021, 10am BST, rebroadcast on 14 April (10am CTT) and 16 April (10am PST) and will feature online versions of the market-leading physical events: CS International and PIC International PLUS a brand new Silicon Semiconductor International Track!

Thanks to the great diversity of the semiconductor industry, we are always chasing new markets and developing a range of exciting technologies.

2021 is no different. Over the last few months interest in deep-UV LEDs has rocketed, due to its capability to disinfect and sanitise areas and combat Covid-19. We shall consider a roadmap for this device, along with technologies for boosting its output.

We shall also look at microLEDs, a display with many wonderful attributes, identifying processes for handling the mass transfer of tiny emitters that hold the key to commercialisation of this technology.

We shall also discuss electrification of transportation, underpinned by wide bandgap power electronics and supported by blue lasers that are ideal for processing copper.

Additional areas we will cover include the development of GaN ICs, to improve the reach of power electronics; the great strides that have been made with gallium oxide; and a look at new materials, such as cubic GaN and AlScN.

Having attracted 1500 delegates over the last 2 online summits, the 3rd event promises to be even bigger and better – with 3 interactive sessions over 1 day and will once again prove to be a key event across the semiconductor and photonic integrated circuits calendar.

So make sure you sign up today and discover the latest cutting edge developments across the compound semiconductor and integrated photonics value chain.

REGISTER FOR FREE

VIEW SESSIONS
Will Future Soldiers Be Made Of Semiconductor?
New Plant To Manufacture Graphene Electronics
EV Group Establishes State-of-the-art Customer Training Facility
Siemens And ASE Enable Next-generation High Density Advanced Package Designs
Belgian Initiative For AI Lung Scan Analysis In Fight Against COVID-19 Goes European
Tower Semiconductor Announced Program Creating An Integrated-Laser-on-Silicon Photonics Foundry Process
U.S. Department Of Defense Partners With GLOBALFOUNDRIES To Manufacture Secure Chips At Fab 8
Imec Demonstrates 20nm Pitch Line/Space Resist Imaging With High-NA EUV Interference Lithography
Cadence Announces $5M Endowment To Advance Research
Can New Advances In CMOS Replace SCMOS Sensors In Biomedical Applications?
GOODFELLOW Confirms Membership In The BSI UK Graphene Group
ITRI And DuPont Inaugurate Semiconductor Materials Lab
Onto Innovation Announces New Inspection Platform
Changes In The Management Board Of 3D-Micromac AG
TEL Introduces Episode UL As The Next Generation Etch Platform
DISCO's Completion Of New Building At Nagano Works Chino Plant
South Korean Point Engineering Chooses ClassOne’s Solstice S8 For Advanced Semiconductor Plating
ASML Reports €14.0 Billion Net Sales
AP&S Expands Management At Beginning Of 2021
Panasonic Microelectronics Web Seminar
SUSS MicroTec Opens New Production Facility In Taiwan
Obducat Receives Order For Fully Automated Resist Processing Tool From A Customer In Asia
K-Space Offers A New Accessory For Their In Situ Metrology Tools
Tescan And 3D-Micromac Collaborate To Increase The Efficiency Of Failure Analysis Workflows

Info
×
Search the news archive

To close this popup you can press escape or click the close icon.
Logo
×
Logo
×
Register - Step 1

You may choose to subscribe to the Silicon Semiconductor Magazine, the Silicon Semiconductor Newsletter, or both. You may also request additional information if required, before submitting your application.


Please subscribe me to:

 

You chose the industry type of "Other"

Please enter the industry that you work in:
Please enter the industry that you work in:
 
X
Info
X
Info
{taasPodcastNotification} Array
Live Event