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News Article

High-k made simpler

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ASM America simplifies high-k and metal integration with first atomically engineered single metal gate stack
The company, a subsidiary of ASM International N.V., announced the availability of a new atomic layer deposition (ALD) process implementing lanthanum oxide (LaOx) and aluminium oxide (AlOx) high-k cap layers that enable 32 nm generation high-k metal gate stacks using a single metal, instead of the two different metals required previously for CMOS. High-k dielectrics, integrated with metal gates enable faster and smaller chips ideally suited for high performance servers and advanced products that require low power such as laptops, PDAs and smart phones.

ASM has pending patents on the new LaOx and AlOx cap processes that address the challenges associated with metal gates at 32 nm geometries and below. Without cap layers, two different metals are needed to create the proper electrical characteristics of both sides (p and n) of the transistor switch. By introducing an ultra thin cap film between the hafnium based gate dielectric and the metal gate, atomic level charges will affect the interaction between the dielectric and the metal. The proper metal film performance can be tuned by varying the cap film’s thickness in a range less than 1 nm, which is only several atomic layers. The process control capability required to achieve such ultra thin films requires the most advanced ALD technology, as offered in ASM’s Pulsar process module. Multiple Pulsar modules can be integrated onto a single Polygon platform to deposit hafnium based films and cap layers sequentially, without exposure to atmosphere, to control the interface between the films.

“Solving the integration challenges for high-k metal gates is a top priority for most of our customers,” explained Glen Wilk, Product Manager for transistor products at ASM. “This new process greatly simplifies the high-k metal gate integration and allows us to support gate first, as well as gate last process flows. ASM now offers ALD processes for the high-k dielectric, cap layer, and metal gate.”
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