News Article
MEMS in a flat pack
Achieving world's thinnest multi chip MEMS package with control IC
Toshiba Corporation announced two optimised packaging technologies for micro electro mechanical systems (MEMS) semiconductor packages that achieve significant cost reductions. The first technology covers encapsulation under normal atmospheric condition, the second a stronger structure for vacuum sealing. Both technologies can be applied at the wafer level, and both have been used to achieve multi chip MEMS packaging with a control IC at a thickness of only 0.8mm, the thinnest yet announced. Both achievements were reported on May 28th and 29th (EST) at the Electronic Components and Technology Conference 2008 held at Florida, U.S.A. from May 28th.
As achieving cost efficiency and high productivity is one of the key objectives of MEMS, there are significant demands for small sized, hermetic cavity packaging technologies. Vacuum sealing is utilised in high speed applications, such as MEMS switch and gyroscopes, but there are various problems with this, including ringing. In applications where high speed is not required, such as use in mobile phones, low cost encapsulation under normal atmospheric condition technology is employed. Toshiba has developed both packaging technologies.
Toshiba will further develop and optimise these technologies toward establishing for practical use.
As achieving cost efficiency and high productivity is one of the key objectives of MEMS, there are significant demands for small sized, hermetic cavity packaging technologies. Vacuum sealing is utilised in high speed applications, such as MEMS switch and gyroscopes, but there are various problems with this, including ringing. In applications where high speed is not required, such as use in mobile phones, low cost encapsulation under normal atmospheric condition technology is employed. Toshiba has developed both packaging technologies.
Toshiba will further develop and optimise these technologies toward establishing for practical use.
