News Article
Design For Manufacturing
To DFM or not to DFM?
You might think that in designing an integrated circuit, optimising for manufacturing yield is the obvious thing to do. “Not always”, argues Wes Hansford of MOSIS.
You might think that in designing an integrated circuit, optimising for manufacturing yield is the obvious thing to do. “Not always”, argues Wes Hansford of MOSIS.
A great deal has been written about the desirability of designing chips with manufacturing in mind, particularly as process geometries shrink and every design parameter becomes more critical. However, a host of factors need to be taken into consideration if the design of a chip is to be optimised for the profit it will generate, rather than simply for a given manufacturing process, as in design for manufacture (DFM). The main cost elements of a device are the silicon itself, test procedures and packaging/assembly. It’s often the case that the silicon cost is only 30% of the total. This means that if you make a huge DFM effort and increase your silicon yield by 30%, you only reduce the overall chip cost by 10%. If you’re making a proprietary chip that costs you $1 and you’re able to sell it for $20, too much focus on DFM may not be worth the investment in time and effort. If you have to sell a chip costing $1 for $1.20, in other words at margins more typical of high volume commodity devices such as Bluetooth transceivers, then maximising silicon yield takes on much greater importance. However, almost everything you do to maximise yield is likely to increase both the power consumption and performance of your device, and extend the device time to market.
What are the main DFM challenges?
At 130nm and larger geometries, silicon fabrication processes are today considered mature. As geometries shrink below this level there are many more factors that need to be taken into account. Digital engineers have had a simpler time of things until now; letting tools that manage design rules do most of the work. But as we go to 90nm and below, even digital designers can no longer leave it to the tools to do everything. They need to become more physically aware. Even many of the latest tools lag behind the pace of change in process technologies. Two different designs that apparently meet the same rules can produce radically different manufacturing yields. The main DFM challenges can be categorised as preventing random and systematic physical defects, and optimising parametric yield.
Physical defects
Mask contamination, stress around shallow trenches and well proximity effects are some of the major causes of physical defects.
Preventing mask contamination becomes more difficult at the smallest geometries. A fab clean room may only be able to filter potentially contaminating particles down to a given size. At 130nm such a particle may not cause any problems but at 65nm it can cause short circuits. The issue is addressed through following layout recommendations and other rules provided in foundry design kits but it essentially comes down to using larger layouts.
Shallow trench isolation (STI) is the main CMOS isolation technique used in sub micron chip design. Trenches are created in the silicon substrate and filled with silicon dioxide around devices (or groups of devices) that need to be isolated to minimise parasitic current flow between them and adjacent elements. However, the technique causes stress in the silicon that adversely affects the performance of both NFETS and PFETS close to the trench edge. Increasing the separation between the trench edge and its adjacent devices is the solution to the problem. Systematic defects can affect both analogue and digital circuits. One example is non uniform pattern density causing dishing on metal layers and creating higher level short circuits.
Parametric factors
Variations in parametric yield, often described as circuit limited yield, occur due to normal process variations. Problems are more common in analogue and RF devices. Components can be created that are within specification but differ from nominal values. Component matching, and therefore performance, is compromised. The issue is primarily addressed through designing circuits to minimise critical matching requirements, and by simulation. The smaller the component, the more sensitive it is likely to be to process variation. For example, a long, wide resistor will be less sensitive than a short, narrow one of the same value.
Parametric yield issues do not scale with chip size or density but are related to the number of process sensitive circuits found in a given design. Monte Carlo analysis, corner simulation and noise isolation analysis are helpful but take time and resources. In sensitive circuits, it is particularly important to perform corner simulations in order the assess chip performance at the limits of its temperature and voltage ratings, for example. Simulating based on nominal values alone can be misleading. Just as when designing to eliminate physical defects, minimising parametric defects can again come down to compromising performance and increasing the chip size.
Statistical analysis
Statistical analysis tools based on models offer a relatively new EDA approach for working out the likelihood of any particular yield limitation arising. Such tools effectively come up with a figure of merit and estimated yield for each design. Input to the tools consists of the design’s database plus statistical information about the process. The latter comes from the fab or the tool vendor. Both fab specific and tool specific information needs to be included to produce a worthwhile statistical yield prediction. These tools are proving useful in improving yields but there are both cost and development time implications in adopting them.
The compromise of DFM
Designing a chip to maximise yield always comes down to compromising performance, power consumption and cost. Greater silicon area is needed because some elements need to be spaced further apart to take account of affects at the atomic level. The resulting longer interconnects add inductance and capacitance which causes compromising speed and performance, and power consumption rises.
In the end DFM is just one more trade off to be taken into account when designing an integrated circuit that will be fabricated in deep sub micron technology. However, there’s one other critical factor to consider. The effort spent trying to maximise yield can extend the time it takes to bring a device to market. This can be the difference between success and failure. For start ups it can be the difference between securing their next round of funding and oblivion.
The MPW opportunity
The use of multi project wafer (MPW) services can be of real value here. By sharing the mask and wafer costs with other designs, it’s possible to create sample quantities of devices, even up to 1000 chips, at less than 10% of the price of using a dedicated wafer run. This creates an opportunity to validate a design and get chips into the hands of customers for early evaluation. Then, if it’s needed, you can put more time into DFM before full production runs are required.
The choice of MPW service provider is important too. You can buy this service directly from a number of foundries or use specialists who work in partnership with the foundries. Such specialists may also be able to provide test and assembly services with proven vendors to minimise the risk of problems during these stages of IC development. Where the foundry owner also produces its own silicon devices, one example being IBM, you have the further benefit of their production experience and all that they have learned from it.
DFM certainly has its place but so does getting to market fast with a device that performs to the target specification. Designing a chip with 100% yield that misses a window of opportunity in the market is little more than an academic project. Using MPWs can help achieve the best outcome in terms of time to market and yield.
What are the main DFM challenges?
At 130nm and larger geometries, silicon fabrication processes are today considered mature. As geometries shrink below this level there are many more factors that need to be taken into account. Digital engineers have had a simpler time of things until now; letting tools that manage design rules do most of the work. But as we go to 90nm and below, even digital designers can no longer leave it to the tools to do everything. They need to become more physically aware. Even many of the latest tools lag behind the pace of change in process technologies. Two different designs that apparently meet the same rules can produce radically different manufacturing yields. The main DFM challenges can be categorised as preventing random and systematic physical defects, and optimising parametric yield.
Physical defects
Mask contamination, stress around shallow trenches and well proximity effects are some of the major causes of physical defects.
Preventing mask contamination becomes more difficult at the smallest geometries. A fab clean room may only be able to filter potentially contaminating particles down to a given size. At 130nm such a particle may not cause any problems but at 65nm it can cause short circuits. The issue is addressed through following layout recommendations and other rules provided in foundry design kits but it essentially comes down to using larger layouts.
Shallow trench isolation (STI) is the main CMOS isolation technique used in sub micron chip design. Trenches are created in the silicon substrate and filled with silicon dioxide around devices (or groups of devices) that need to be isolated to minimise parasitic current flow between them and adjacent elements. However, the technique causes stress in the silicon that adversely affects the performance of both NFETS and PFETS close to the trench edge. Increasing the separation between the trench edge and its adjacent devices is the solution to the problem. Systematic defects can affect both analogue and digital circuits. One example is non uniform pattern density causing dishing on metal layers and creating higher level short circuits.
Parametric factors
Variations in parametric yield, often described as circuit limited yield, occur due to normal process variations. Problems are more common in analogue and RF devices. Components can be created that are within specification but differ from nominal values. Component matching, and therefore performance, is compromised. The issue is primarily addressed through designing circuits to minimise critical matching requirements, and by simulation. The smaller the component, the more sensitive it is likely to be to process variation. For example, a long, wide resistor will be less sensitive than a short, narrow one of the same value.
Parametric yield issues do not scale with chip size or density but are related to the number of process sensitive circuits found in a given design. Monte Carlo analysis, corner simulation and noise isolation analysis are helpful but take time and resources. In sensitive circuits, it is particularly important to perform corner simulations in order the assess chip performance at the limits of its temperature and voltage ratings, for example. Simulating based on nominal values alone can be misleading. Just as when designing to eliminate physical defects, minimising parametric defects can again come down to compromising performance and increasing the chip size.
Statistical analysis
Statistical analysis tools based on models offer a relatively new EDA approach for working out the likelihood of any particular yield limitation arising. Such tools effectively come up with a figure of merit and estimated yield for each design. Input to the tools consists of the design’s database plus statistical information about the process. The latter comes from the fab or the tool vendor. Both fab specific and tool specific information needs to be included to produce a worthwhile statistical yield prediction. These tools are proving useful in improving yields but there are both cost and development time implications in adopting them.
The compromise of DFM
Designing a chip to maximise yield always comes down to compromising performance, power consumption and cost. Greater silicon area is needed because some elements need to be spaced further apart to take account of affects at the atomic level. The resulting longer interconnects add inductance and capacitance which causes compromising speed and performance, and power consumption rises.
In the end DFM is just one more trade off to be taken into account when designing an integrated circuit that will be fabricated in deep sub micron technology. However, there’s one other critical factor to consider. The effort spent trying to maximise yield can extend the time it takes to bring a device to market. This can be the difference between success and failure. For start ups it can be the difference between securing their next round of funding and oblivion.
The MPW opportunity
The use of multi project wafer (MPW) services can be of real value here. By sharing the mask and wafer costs with other designs, it’s possible to create sample quantities of devices, even up to 1000 chips, at less than 10% of the price of using a dedicated wafer run. This creates an opportunity to validate a design and get chips into the hands of customers for early evaluation. Then, if it’s needed, you can put more time into DFM before full production runs are required.
The choice of MPW service provider is important too. You can buy this service directly from a number of foundries or use specialists who work in partnership with the foundries. Such specialists may also be able to provide test and assembly services with proven vendors to minimise the risk of problems during these stages of IC development. Where the foundry owner also produces its own silicon devices, one example being IBM, you have the further benefit of their production experience and all that they have learned from it.
DFM certainly has its place but so does getting to market fast with a device that performs to the target specification. Designing a chip with 100% yield that misses a window of opportunity in the market is little more than an academic project. Using MPWs can help achieve the best outcome in terms of time to market and yield.
