News Article
Etch
The leading etch
Via profile and integration requirements are critical in TSV etch. Steve Lassig of Lam Research Corporation describes the importance of etch rate for the optimum TSV etch solution.
Via profile and integration requirements are critical in TSV etch. Steve Lassig of Lam Research Corporation describes the importance of etch rate for the optimum TSV etch solution.
The prospect of etching through tens or hundreds of microns of silicon can seem rather daunting when compared to typical interconnect vias that are, at most, a micron or two deep. While a high etch rate will increase process throughput and have considerable influence on the cost of implementing through silicon via (TSV) technologies, on closer examination, considerations such as integration and profile requirements play roles of equal or greater importance in determining overall cost and success. Optimising etch rate while meeting critical profile and undercut requirements and being mindful of the need to also etch multi film stacks will be essential to cost effective implementation of TSV technologies.
While through silicon via is the accepted industry term, this type of via typically penetrates multiple materials, including oxides, nitrides, low-k dielectrics, polysilicon and often metals in addition to the silicon substrate.
One of the key considerations of the integration scheme is how to etch through these different layers: use separate etch modules for each layer type (metal, dielectric and silicon) to complete the required etch sequence or use an in situ approach wherein a single module performs multiple functions, significantly reducing capital costs.
The integration scheme must also consider the TSV formation process in relation to the overall manufacturing process flow. For example, whether photoresist or hardmask patterning is used (in most cases, photoresist is the preferred masking material); the profile requirements for subsequent fill, and electrical specifications should all be considered. All of these areas will significantly impact which chemistries and etch approach are best.
Profile requirements control the specific geometry of the via, ultimately ensuring their electrical functionality, yield and reliability. Requirements include:
1) a controlled taper, which facilitates complete filling in high aspect ratio vias;
2) managing the undercut of the silicon substrate below the overlying dielectric, which can otherwise interfere with the continuity of the subsequently deposited layers;
3) minimising sidewall roughness, which can also interfere with continuity and increase the required thickness of the dielectric liner;
4) minimising profile tilting, to ensure proper alignment when die are finally stacked and bonded; and
5) ensuring cross wafer uniformity of depth, especially critical for 300mm wafer size.
Approaches for high silicon etch rates
Plasma assisted etching of silicon is a complex process that combines the isotropic chemical action of reactive neutral species, chemical passivation of the etched surface, and the anisotropic physical action of charged species to provide highly directional etching of the passivation layer. The plasma creates both the reactive neutrals and the ions. Neutral species reach the wafer surface by diffusion. Ions are accelerated toward the wafer by a bias voltage between the plasma and the wafer.
A fluorine containing plasma using sulphur hexafluoride (SF6) etches silicon with a very high etch rate and has been used for deep silicon patterning for integrated circuits and micro electromechanical systems (MEMS) [1–8]. Silicon etching with SF6 is highly chemical and produces a very isotropic (round) profile in the absence of RF bias and sidewall passivation [9]. There are two process approaches for providing anisotropic or tapered etch profiles. Both use RF bias to accelerate ions vertically toward the surface; hence, the main difference is in the methods of providing the sidewall passivation.
The first method, referred to here as the steady state process, relies on additive gasses to SF6 plasma chemistry, such as O2 and HBr, which have been used and modelled extensively [9,10]. When oxygen is added to SF6, a thin silicon dioxide layer is formed on the etched sidewall to inhibit lateral etch, thus promoting anisotropic profile shape [2, 9] (see Figure 1a). Etch rates will depend on via size, total exposed silicon area, and profile requirements. Higher pressure processes lead to higher etch rates, typically at the cost of increased profile bowing, mask undercut, and cross wafer non uniformity.
Due to the use of oxygen and high bias, typically about two hundred volts, a steady state process has relatively low selectivity to photoresist compared to the Bosch process [8] described next. Consequently, the steady state process is commonly employed using a hard mask such as a deposited oxide to improve selectivity. This adds additional cost and complexity to the integration scheme. The Bosch process, a time modulated approach in which fluorocarbons provide the needed passivation, is employed more frequently, especially for vias with high aspect ratios. The Bosch process rapidly switches between silicon etch steps with SF6 and polymer deposition steps using C4F8 (see Figure 1b).
This allows much higher selectivity to photoresist, higher aspect ratios, and better control of undercut at high etch rates. Like the steady state process, etch rate will depend on via size, total exposed silicon area, and profile requirements. The Bosch process can create vias with very high aspect ratios, even at small diameters. Figure 2 shows some examples of such TSVs etched into 300mm wafers patterned with photoresist.
Cross wafer uniformity of etch rate and via tilt are critical for TSVs. Most integration schemes etch the via blindly to a presumed depth. At some point later in the process, after the vias have been filled, the wafer is thinned by removing material from the backside, exposing the TSV. If the etch rate varies, some vias may not be revealed, or the variation in exposed TSV may create subsequent bonding problems.
If the vias are tilted, their location on the backside will be shifted, possibly causing misalignment and yield loss. Uniformity is primarily a function of chamber design, not easily corrected by manipulating process parameters.
System designs using a capacitively coupled plasma (CCP) or Transformer Coupled Plasma high density plasma source produce a planar plasma in a disc shape and are easier to scale to larger wafer sizes. Inductively coupled plasma (ICP) sources typically are “down stream” in that the plasma source appears almost as a point source located some distance from the wafer surface, making it more difficult to maintain uniform conditions across the wafer. Non uniformity usually appears as a radial variation in via depth and tilt.
Integration Requirements:
In Situ Processing
The importance of integration requirements is made apparent by the large number of integration schemes currently under investigation [11]. Sometimes it seems that there are almost as many different schemes as there are companies involved in TSV development. The schemes are often classified as via first or via last, defined by whether the vias are etched before or after conventional back end of line (BEOL) processing is completed. Each of these classifications includes numerous variations. Although the name “through silicon via” directs attention explicitly to silicon, almost every integration scheme currently under consideration requires the via to penetrate one or more other materials before reaching the silicon substrate.
In the simplest case, it may be only a single layer of oxide. At the other extreme, the stack may include multiple layers of oxide, nitride, polysilicon and even metals. The etch process (or processes) chosen to address the presence of multiple materials can impact overall process throughput and complexity. At one extreme, the TSV etch process could require a different tool for each material in the stack, with multiple transfers and perhaps intermediate cleaning and masking steps in between.
Though each tool might offer optimal performance on its particular layer, overall performance could easily be inferior to an in situ approach capable of etching the entire stack in a single tool.
In the case of the via first approach, where the TSV is etched after the front end of the line (devices) have been completed, there will be some dielectric, and possibly plasma oxide and nitride, to be etched prior to the silicon etch. Figure 3 shows such an example on a 300mm wafer. Here the wafer has 1μm thick oxide and 10μm CD vias that were patterned with photoresist. In a single wafer pass, the via was etched through the oxide, then into the silicon to a depth of 60μm. Such features with minimal undercut and slight taper are ideal for subsequent filling with no voids. Even with the same etch rates, system uptime, and comparable system costs, the in situ approach can save up to 50 percent in capital costs over a separate chamber approach.
In the case of the via last approach, where the TSV is fabricated after front end wafer processing is completed, the via etch will have to open multiple films prior to the deep silicon etch. These films can range from conductive to dielectric materials. As a demonstration, we fabricated 300mm wafers with 3μm of silicon dioxide and 1μmof aluminium, then patterned them with 30μm CD vias using 25μm thick photoresist. The films were etched in situ and resulted in relatively smooth sidewalls and minimal undercut (Figure 4). In a production environment, the in situ etch would be followed by a strip and passivation in a separate strip chamber prior to exposure to atmosphere to minimize the potential for corrosion. Again, the in situ approach results in substantial capital cost reduction compared to a separate chamber approach.
Several aspects of system design determine the ability to support in situ processing and cleaning. In situ processing requires precise, flexible control of process gases and etch conditions over an extended range of values in order to accommodate the widest range of process requirements. CCP systems are generally not suitable for in situ processing since they require electrode materials that are specific to the material being etched and have only limited ability for independent control of bias and plasma generating fields. Both TCP and ICP systems decouple bias and plasma RF fields, but the large chambers required for ICP make in situ cleaning difficult. TCP technology’s combination of compact chamber design and process flexibility makes it ideal for in situ processing and cleaning.
Conclusion
Etch rate is only one of many characteristics that must be considered in determining the optimum TSV etch solution. It has value as a figure of merit only when qualified by appropriate via profile requirements. In situ processing can improve throughput, reduce capital costs, and reduce cycle time by etching multiple overlaying layers and the silicon substrate in a single etch module. In situ cleaning enables in situ processing and improves process repeatability and tool availability.
References:
[1] A. A. Ayon, R. A. Braff, R. Bayt, H. H. Sawin, and M. A. Schmidt, J. Electrochem. Soc. 146, 2730 (1999).
[2] R. Dagostino and D. L. Flamm, J. Appl. Phys. 52, 162 (1981).
[3] D. L. Flamm, V. M. Donnelly, and J. A. Mucha, J. Appl. Phys. 52, 3633 (1981).
[4] T. Syau, B. J. Baliga, and R. W. Hamaker, J. Electrochem. Soc. 138, 3076 (1991).
[5] C. P. Demic, K. K. Chan, and J. Blum, J. Vac. Sci. Technol. B 10, 1105 (1992).
[6] H. F. Winters and J. W. Coburn, Surf. Sci. Rep. 14, 161 (1992).
[7] R. D. Mansano, P. Verdonck, and H. S. Maciel, Appl. Surf. Sci. 101, 583 (1996).
[8] F. Laermer, A. Schilp, K. Funk, M. Offenberg, Proceedings of MEMS ’99, 211 (1999)
[9] R. J. Belen, S. Gomez, M. Kielbauch, D. Cooperberg, and E. S. Aydil, J. Vac. Sci. Technol. A 23(1), 99 (2005)
[10]R. J. Belen, S. Gomez, M. Kielbauch, and E. S. Aydil, J. Vac. Sci. Technol. A 24(2), 350 (2006)
[11] S. Lassig, Solid State Technology December, 2007
Acknowledgement
The author thanks the 3D Integration Group at Lam Research for the superb process development and scanning electron microscopy for this article.
While through silicon via is the accepted industry term, this type of via typically penetrates multiple materials, including oxides, nitrides, low-k dielectrics, polysilicon and often metals in addition to the silicon substrate.
One of the key considerations of the integration scheme is how to etch through these different layers: use separate etch modules for each layer type (metal, dielectric and silicon) to complete the required etch sequence or use an in situ approach wherein a single module performs multiple functions, significantly reducing capital costs.
The integration scheme must also consider the TSV formation process in relation to the overall manufacturing process flow. For example, whether photoresist or hardmask patterning is used (in most cases, photoresist is the preferred masking material); the profile requirements for subsequent fill, and electrical specifications should all be considered. All of these areas will significantly impact which chemistries and etch approach are best.
Profile requirements control the specific geometry of the via, ultimately ensuring their electrical functionality, yield and reliability. Requirements include:
1) a controlled taper, which facilitates complete filling in high aspect ratio vias;
2) managing the undercut of the silicon substrate below the overlying dielectric, which can otherwise interfere with the continuity of the subsequently deposited layers;
3) minimising sidewall roughness, which can also interfere with continuity and increase the required thickness of the dielectric liner;
4) minimising profile tilting, to ensure proper alignment when die are finally stacked and bonded; and
5) ensuring cross wafer uniformity of depth, especially critical for 300mm wafer size.
Approaches for high silicon etch rates
Plasma assisted etching of silicon is a complex process that combines the isotropic chemical action of reactive neutral species, chemical passivation of the etched surface, and the anisotropic physical action of charged species to provide highly directional etching of the passivation layer. The plasma creates both the reactive neutrals and the ions. Neutral species reach the wafer surface by diffusion. Ions are accelerated toward the wafer by a bias voltage between the plasma and the wafer.
A fluorine containing plasma using sulphur hexafluoride (SF6) etches silicon with a very high etch rate and has been used for deep silicon patterning for integrated circuits and micro electromechanical systems (MEMS) [1–8]. Silicon etching with SF6 is highly chemical and produces a very isotropic (round) profile in the absence of RF bias and sidewall passivation [9]. There are two process approaches for providing anisotropic or tapered etch profiles. Both use RF bias to accelerate ions vertically toward the surface; hence, the main difference is in the methods of providing the sidewall passivation.
The first method, referred to here as the steady state process, relies on additive gasses to SF6 plasma chemistry, such as O2 and HBr, which have been used and modelled extensively [9,10]. When oxygen is added to SF6, a thin silicon dioxide layer is formed on the etched sidewall to inhibit lateral etch, thus promoting anisotropic profile shape [2, 9] (see Figure 1a). Etch rates will depend on via size, total exposed silicon area, and profile requirements. Higher pressure processes lead to higher etch rates, typically at the cost of increased profile bowing, mask undercut, and cross wafer non uniformity.
Due to the use of oxygen and high bias, typically about two hundred volts, a steady state process has relatively low selectivity to photoresist compared to the Bosch process [8] described next. Consequently, the steady state process is commonly employed using a hard mask such as a deposited oxide to improve selectivity. This adds additional cost and complexity to the integration scheme. The Bosch process, a time modulated approach in which fluorocarbons provide the needed passivation, is employed more frequently, especially for vias with high aspect ratios. The Bosch process rapidly switches between silicon etch steps with SF6 and polymer deposition steps using C4F8 (see Figure 1b).
This allows much higher selectivity to photoresist, higher aspect ratios, and better control of undercut at high etch rates. Like the steady state process, etch rate will depend on via size, total exposed silicon area, and profile requirements. The Bosch process can create vias with very high aspect ratios, even at small diameters. Figure 2 shows some examples of such TSVs etched into 300mm wafers patterned with photoresist.
Cross wafer uniformity of etch rate and via tilt are critical for TSVs. Most integration schemes etch the via blindly to a presumed depth. At some point later in the process, after the vias have been filled, the wafer is thinned by removing material from the backside, exposing the TSV. If the etch rate varies, some vias may not be revealed, or the variation in exposed TSV may create subsequent bonding problems.
If the vias are tilted, their location on the backside will be shifted, possibly causing misalignment and yield loss. Uniformity is primarily a function of chamber design, not easily corrected by manipulating process parameters.
System designs using a capacitively coupled plasma (CCP) or Transformer Coupled Plasma high density plasma source produce a planar plasma in a disc shape and are easier to scale to larger wafer sizes. Inductively coupled plasma (ICP) sources typically are “down stream” in that the plasma source appears almost as a point source located some distance from the wafer surface, making it more difficult to maintain uniform conditions across the wafer. Non uniformity usually appears as a radial variation in via depth and tilt.
Integration Requirements:
In Situ Processing
The importance of integration requirements is made apparent by the large number of integration schemes currently under investigation [11]. Sometimes it seems that there are almost as many different schemes as there are companies involved in TSV development. The schemes are often classified as via first or via last, defined by whether the vias are etched before or after conventional back end of line (BEOL) processing is completed. Each of these classifications includes numerous variations. Although the name “through silicon via” directs attention explicitly to silicon, almost every integration scheme currently under consideration requires the via to penetrate one or more other materials before reaching the silicon substrate.
In the simplest case, it may be only a single layer of oxide. At the other extreme, the stack may include multiple layers of oxide, nitride, polysilicon and even metals. The etch process (or processes) chosen to address the presence of multiple materials can impact overall process throughput and complexity. At one extreme, the TSV etch process could require a different tool for each material in the stack, with multiple transfers and perhaps intermediate cleaning and masking steps in between.
Though each tool might offer optimal performance on its particular layer, overall performance could easily be inferior to an in situ approach capable of etching the entire stack in a single tool.
In the case of the via first approach, where the TSV is etched after the front end of the line (devices) have been completed, there will be some dielectric, and possibly plasma oxide and nitride, to be etched prior to the silicon etch. Figure 3 shows such an example on a 300mm wafer. Here the wafer has 1μm thick oxide and 10μm CD vias that were patterned with photoresist. In a single wafer pass, the via was etched through the oxide, then into the silicon to a depth of 60μm. Such features with minimal undercut and slight taper are ideal for subsequent filling with no voids. Even with the same etch rates, system uptime, and comparable system costs, the in situ approach can save up to 50 percent in capital costs over a separate chamber approach.
In the case of the via last approach, where the TSV is fabricated after front end wafer processing is completed, the via etch will have to open multiple films prior to the deep silicon etch. These films can range from conductive to dielectric materials. As a demonstration, we fabricated 300mm wafers with 3μm of silicon dioxide and 1μmof aluminium, then patterned them with 30μm CD vias using 25μm thick photoresist. The films were etched in situ and resulted in relatively smooth sidewalls and minimal undercut (Figure 4). In a production environment, the in situ etch would be followed by a strip and passivation in a separate strip chamber prior to exposure to atmosphere to minimize the potential for corrosion. Again, the in situ approach results in substantial capital cost reduction compared to a separate chamber approach.
Several aspects of system design determine the ability to support in situ processing and cleaning. In situ processing requires precise, flexible control of process gases and etch conditions over an extended range of values in order to accommodate the widest range of process requirements. CCP systems are generally not suitable for in situ processing since they require electrode materials that are specific to the material being etched and have only limited ability for independent control of bias and plasma generating fields. Both TCP and ICP systems decouple bias and plasma RF fields, but the large chambers required for ICP make in situ cleaning difficult. TCP technology’s combination of compact chamber design and process flexibility makes it ideal for in situ processing and cleaning.
Conclusion
Etch rate is only one of many characteristics that must be considered in determining the optimum TSV etch solution. It has value as a figure of merit only when qualified by appropriate via profile requirements. In situ processing can improve throughput, reduce capital costs, and reduce cycle time by etching multiple overlaying layers and the silicon substrate in a single etch module. In situ cleaning enables in situ processing and improves process repeatability and tool availability.
References:
[1] A. A. Ayon, R. A. Braff, R. Bayt, H. H. Sawin, and M. A. Schmidt, J. Electrochem. Soc. 146, 2730 (1999).
[2] R. Dagostino and D. L. Flamm, J. Appl. Phys. 52, 162 (1981).
[3] D. L. Flamm, V. M. Donnelly, and J. A. Mucha, J. Appl. Phys. 52, 3633 (1981).
[4] T. Syau, B. J. Baliga, and R. W. Hamaker, J. Electrochem. Soc. 138, 3076 (1991).
[5] C. P. Demic, K. K. Chan, and J. Blum, J. Vac. Sci. Technol. B 10, 1105 (1992).
[6] H. F. Winters and J. W. Coburn, Surf. Sci. Rep. 14, 161 (1992).
[7] R. D. Mansano, P. Verdonck, and H. S. Maciel, Appl. Surf. Sci. 101, 583 (1996).
[8] F. Laermer, A. Schilp, K. Funk, M. Offenberg, Proceedings of MEMS ’99, 211 (1999)
[9] R. J. Belen, S. Gomez, M. Kielbauch, D. Cooperberg, and E. S. Aydil, J. Vac. Sci. Technol. A 23(1), 99 (2005)
[10]R. J. Belen, S. Gomez, M. Kielbauch, and E. S. Aydil, J. Vac. Sci. Technol. A 24(2), 350 (2006)
[11] S. Lassig, Solid State Technology December, 2007
Acknowledgement
The author thanks the 3D Integration Group at Lam Research for the superb process development and scanning electron microscopy for this article.
