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Anniversary results for NanoCMOS
Grid technology tackles the impact of CMOS variability on design. Professor Asen Asenov of Glasgow University explains the development.
Grid technology tackles the impact of CMOS variability on design. Professor Asen Asenov of Glasgow University explains the development.
Three papers accepted almost simultaneously in IEEE Electron Device Letters, a journal for rapid communication in the area of CMOS devices and technology, mark the first anniversary of the EPSRC funded UK e-Science pilot project “Meeting the Design Challenges of NanoCMOS electronics” (NanoCMOS). The project led by Professor Asen Asenov from Glasgow University is developing Grid based solutions to assist the design of giga transistor chips in the presence of statistical transistor variability introduced by the discreteness of charge and matter, now perceived as a major bottleneck for scaling and integration in future manufacturing of devices.
The first year of the project was focused on the development of supercomputing grid enabled simulation tools capable of handling the massive amount of simulations required for the accurate prediction of statistical variability in future nanoscale transistors. These are urgently needed to address forthcoming design challenges associated with rapidly increasing statistical variability, and to allow early development of variability aware design tools and algorithms. The accurate forecasting of statistical variability requires 3D simulations of huge numbers of transistors, which differ on the atomic scale due to random discrete dopants, line edge roughness and poly silicon gate granularity. The 3D simulation of a single transistor can take anywhere between several hours and several days. The Grid technology developed at in NanoCMOS allows the simulation of literally thousands of transistors to be carried out simultaneously on hundreds and thousands of processors provided by Grid connected computers making it possible to study these phenomena on realistic timescales.
The first two papers “Quantitative Evaluation of Statistical Variability Sources in a 45nm Technological Node LP N-MOSFET” and “Origin of the Asymmetry in the Magnitude of the Statistical Variability of n-and p-channel Poly Si Gate Bulk MOSFETs” demonstrate the accuracy and the precision of the developed simulation tools, showing excellent agreement of simulation results with the statistical distributions of the threshold voltages measured on 45 nm technology generation n-channel and p-channel CMOS transistors developed by ST Microelectronics. The papers highlight the role of the poly silicon gate granularity (illustrated in Fig. 1) which enhances the statistical variability in n-channel transistors but has little effect on their p-channel counterparts due to specific electronic structure of the grain boundary interface.
The third paper demonstrates the true potential of the Grid technology. It reports ground breaking results; undertaking over 100,000 3D simulations of a 35 nm channel length transistor under the influence of random discrete dopants. Such simulations, would require more than 20 years using a single processor workstation, but were accomplished in less than a week on the ScotGrid resource. The simulations revealed the true nature of random dopant induced threshold voltage distributions, which, contrary to common belief, are not Gaussian. The detailed information obtained at the tails of the distribution is very important for the design of variability sensitive circuits like SRAM which are already designed to 7-8 sigma levels.
In the remaining 3 years of the project, Grid technology will be developed to propagate this device variability information up the design verification chain allowing simulation and optimisation of large statistical circuits, subsystems and SoC.
References:
Notes: The three papers will appear in the following issues of IEEE Electron Device Letters:
EDL MS #4785 - “Quantitative Evaluation of Statistical Variability Sources in a 45nm Technological Node LP N-MOSFET” EDL June 2008 Vol. 29, No. 6, pp 609 - 611
EDL-2008-04-0384.R1 - “Origin of the Asymmetry in the Magnitude of the Statistical Variability of n- and p-channel Poly Si Gate Bulk MOSFETs” scheduled for EDL August 2008, Vol. 29, No. 8
EDL-2008-04-0367 - “Accurate Statistical Description of Random Dopant Induced Threshold Voltage Variability” scheduled for EDL August 2008, Vol. 29, No. 8
The first year of the project was focused on the development of supercomputing grid enabled simulation tools capable of handling the massive amount of simulations required for the accurate prediction of statistical variability in future nanoscale transistors. These are urgently needed to address forthcoming design challenges associated with rapidly increasing statistical variability, and to allow early development of variability aware design tools and algorithms. The accurate forecasting of statistical variability requires 3D simulations of huge numbers of transistors, which differ on the atomic scale due to random discrete dopants, line edge roughness and poly silicon gate granularity. The 3D simulation of a single transistor can take anywhere between several hours and several days. The Grid technology developed at in NanoCMOS allows the simulation of literally thousands of transistors to be carried out simultaneously on hundreds and thousands of processors provided by Grid connected computers making it possible to study these phenomena on realistic timescales.
The first two papers “Quantitative Evaluation of Statistical Variability Sources in a 45nm Technological Node LP N-MOSFET” and “Origin of the Asymmetry in the Magnitude of the Statistical Variability of n-and p-channel Poly Si Gate Bulk MOSFETs” demonstrate the accuracy and the precision of the developed simulation tools, showing excellent agreement of simulation results with the statistical distributions of the threshold voltages measured on 45 nm technology generation n-channel and p-channel CMOS transistors developed by ST Microelectronics. The papers highlight the role of the poly silicon gate granularity (illustrated in Fig. 1) which enhances the statistical variability in n-channel transistors but has little effect on their p-channel counterparts due to specific electronic structure of the grain boundary interface.
The third paper demonstrates the true potential of the Grid technology. It reports ground breaking results; undertaking over 100,000 3D simulations of a 35 nm channel length transistor under the influence of random discrete dopants. Such simulations, would require more than 20 years using a single processor workstation, but were accomplished in less than a week on the ScotGrid resource. The simulations revealed the true nature of random dopant induced threshold voltage distributions, which, contrary to common belief, are not Gaussian. The detailed information obtained at the tails of the distribution is very important for the design of variability sensitive circuits like SRAM which are already designed to 7-8 sigma levels.
In the remaining 3 years of the project, Grid technology will be developed to propagate this device variability information up the design verification chain allowing simulation and optimisation of large statistical circuits, subsystems and SoC.
References:
Notes: The three papers will appear in the following issues of IEEE Electron Device Letters:
EDL MS #4785 - “Quantitative Evaluation of Statistical Variability Sources in a 45nm Technological Node LP N-MOSFET” EDL June 2008 Vol. 29, No. 6, pp 609 - 611
EDL-2008-04-0384.R1 - “Origin of the Asymmetry in the Magnitude of the Statistical Variability of n- and p-channel Poly Si Gate Bulk MOSFETs” scheduled for EDL August 2008, Vol. 29, No. 8
EDL-2008-04-0367 - “Accurate Statistical Description of Random Dopant Induced Threshold Voltage Variability” scheduled for EDL August 2008, Vol. 29, No. 8
