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Accellera board approves new version of analogue, mixed signal standard

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Standard unifies Verilog HDL standard IEEE Std. 1364 with Accellera’s AMS standard, results in easier implementations by tool developers and more efficient top down verification.
Accellera, the electronics industry organisation focused on Electronic Design Automation (EDA) standards, announced today that its Board of Directors and Technical Committee members, systems, semiconductor and design tool companies, approved a new version of its Verilog-Analog Mixed-Signal (AMS) standard, Verilog-AMS 2.3, as an Accellera standard for analogue and mixed signal design and simulation. The new Verilog-AMS standard unifies the Verilog-AMS 2.2 specification with the IEEE Std. 1364-2005 or Verilog hardware description language (HDL) standard.

Verilog-AMS 2.3 enables users to develop standard and tightly integrated Verilog-AMS modules and allows EDA software tool developers to implement EDA tools without ambiguities in the language interpretation.

Verilog-AMS 2.3 encompasses analogue and mixed signal extensions to IEEE Std. 1364, which is widely used today for digital circuit design and verification. The previous Accellera Verilog-AMS standard, Verilog-AMS 2.2, was approved in 2005.

“The Verilog-AMS 2.3 language release is an important milestone for our technical committee and the industry at large,” said Shrenik Mehta, Accellera chairman. “A unified Verilog-AMS language integrated with the IEEE Verilog standard improves AMS design and will result in an increased acceptance of the standard.”

"Accellera’s AMS standard is a reality due to the enormous efforts of our Subcommittee members, who are driven by the goal to improve the productivity of AMS designers and the quality of mixed signal designs," added Sri Chandrasekaran, Accellera’s Verilog-AMS technical subcommittee chairman.
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