German and Austrian scientists report theoretical calculations of interface formation for proposed high-k gate oxide strontium titanate on silicon (Nature, January 1, 2004). The researchers propose an interface structure that is "quite different and much simpler than previously assumed". Two types of interface are seen in the calculations that can be formed selectively in the absence of an interfacial silicon dioxide layer.
STMicroelectronics acquired UK wireless-LAN chip developer Synad Technologies. The acquired company has a full dual-band (2.4/5GHz) multi-standard CMOS production-ready chipset and reference design, and software suites for both wireless-LAN access point and client applications. The products are designed for a 180nm CMOS process.
Market researcher Gartner has released world semiconductor capital and equipment spending estimates for 2004. Capital spending is set to increase 27.9% on 2003’s $28.94bn to $37.11bn. Capital equipment is expected to see an even bigger leap of 35.9% from $21.74bn to $29.54bn.
Infineon Technologies plans to spin off its European real estate and facility management activities to Dussmann of Berlin. Further, Air Liquide (Duesseldorf) and Kinetics (Eschau/Hobbach) will take over operation of gas and chemicals supply and distribution at Infineon’s European production sites. Relevant agreements have already been signed. The relevant functions will be transferred to Infineon’s outsourcing partners in H1 2004.
The (TUM) Walter Schottky Institute (WSI) has ordered an AIX 200/4 MOCVD system from Aixtron. The WSI will use the new system for studies on long wavelength vertical cavity surface emitting laser (VCSEL) layer structures with a unique buried tunnel junction (BTJ) architecture.
Wacker Siltronic has successfully started the first processing step at its new 300mm wafer fab at Freiberg in the German state of Saxony. The first 300 mm monocrystalline ingot was sliced into thin wafers on schedule, December 3, 2003.
ASML MaskTools and Photronics plan to jointly develop a production-ready, mask making infrastructure for ASML MaskTools’ patented chromeless phase lithography (CPL) technology. CPL is a single mask, single exposure resolution enhancement technique that enables low k1 lithography at advanced technology nodes.
The UK’s Institute of Nanotechnology and the National Physical Laboratory (NPL) are linking up to support UK companies interested in applying for nanotechnology research and development funds under the EU Framework 6 (FP6) programme.
The Advanced Silicon Processing & Manufacturing Technologies (ASP&MT) industry based training (education) programme achieved its first Masters degree. The University of Edinburgh conferred the degree on Paul Sermanni (pictured with director of studies Dr Les Haworth and Professor Anthony Walton). The successful graduate is a Device section manager at Motorola, East Kilbride, Scotland.
IMEC says that it has successfully demonstrated the use of high-k dielectrics and metal gates to values below 1nm. The European research centre believes that this level of electrical performance removes one of the industry's 'red brick walls' to advancing semiconductor technology. The research team used metal gates to overcome the problems imposed by the interaction between high-k materials with the commonly used polysilicon electrode.
Europe’s recently created "Photovoltaics Technology Research Advisory Council" aims to challenge Japanese dominance in the market. The initiative of the European Commission (EC) involves 18 members representing all the major players in this technology. The committee first met on December 4, 2003.
Malaysian company Unisem has entered into a conditional sale and purchase agreement to acquire the entire issued and paid-up share capital of Atlantic Technology Holdings (UK).
Atlantic is a European independent mixed-signal and RF test and assembly service provider. Test capabilities include high frequency devices in the range 2.5-6.0GHz.
International SEMATECH (ISMT) engineers have qualified a high-k baseline process with a 70nm transistor length (85nm technology node). The baseline process uses a promising new material and will be used as a comparison standard for ongoing metal gate development.
SEZ is expanding its portfolio of spin-process substrate-etch tools to address demand for thinner, higher-performing IC packages. The new Galileo system (GL-210) uses SEZ's wet spin-processing technology in a single-wafer system that delivers wafer thinning, surface conditioning and stress relief. Two key sectors for the technology are highlighted - back-end assembly/packaging, and front-end wafer manufacturing.
Soitec is to enter into an agreement with Seika, its long-time distribution partner in Japan, to form a Japanese joint venture. The new company will provide UNIBOND silicon-on-insulator (SOI) wafers and other engineered substrates manufactured using Soitec's Smart Cut technology. Apart from Japan, the venture will also serve Korea and China with a full direct sales and support organisation.
UMC claims to be the first foundry to use chromeless (Cr-less) phase-shift mask technology for functional customer products at the 90nm node. Due to the excellent results, UMC says it is also considering 193nm Cr-less phase-shift mask technology for migration to the 65nm generation.
Nikon has completed capability studies on fundamental technologies related to immersion lithography. The feasibility studies have taken half a year. The company says that it has found no showstopper that might prevent the technology’s realisation.
A judgment invalidating five of six claims in Soitec's primary Smart-Cut US patent (No.5,374,564) has been affirmed by a US federal appeal court. However, the appeal court specifically upheld the finding that the defendant SiGen infringed a key claim of the patent as well as the award to Soitec of close to $5mn million in damages (including running interest) for the infringement. The original verdict came from the Massachusetts US district court on April 1, 2002.
Soitec is expanding manufacturing capabilities of strained silicon-on-insulator (SOI) wafers. Specifically, the company is installing epitaxial equipment in its pilot line facility and a full Smart Cut strained-silicon germanium-on-insulator (SGOI) and strained-silicon-on-insulator (sSOI) manufacturing line at its Bernin II site in France.
ASML Holding expects its order backlog at December 31, 2003, to be greater than its previously disclosed order backlog of 91 systems as of September 28, 2003. The company bases this on customer orders as of December 1, 2003, and anticipated system shipments through to year-end. At the time of its Q3 2003 results, ASML had said that backlog could decline in Q4 2003.