YorChip announces patent-pending Universal PHY for Open Chiplets
Single PHY for Standard and advanced packaging with support for older and advanced nodes.
YorChip, Inc. announces development of a Universal PHYTM enabling customers to develop Open Chiplets and ASIC solutions using a single die-to-die PHY. Currently, the popular UCIe standard has three incompatible versions for different packaging solutions. As each Chiplet costs Millions of dollars to develop and productize this incompatibility has been a major roadblock to an Open Chiplet economy, as developers need to be sure of a long revenue window before funding development.
Chiplets represents multi-billion-dollar market potential – according to Transparency Market Research, the Chiplet market is expected to reach more than US$47 Billion by 2031, representing one of the fastest growing segments of the semiconductor industry at more than 40% CAGR from 2021 to 2031. This growth was expected to be enabled by the considerable cost reduction and improved yields Chiplets will enable as compared to traditional system-on-chip (SOC) designs but has been limited by high packaging and PHY costs to HPC markets.
YorChip’s CEO and founder, Kash Johal, said, “We are excited to launch our patent-pending Universal PHYTM that supports both UCIe (all three versions) and the upcoming BOW.Flexi standard. The key innovation here is to be able to support a wide range of packaging options with a single PHY architecture giving designers a single solution for different applications and Markets. This PHY is designed to be portable to older and advanced nodes and will be available to ASIC customers at no extra cost as part of their ASIC NRE.”
YorChip’s CTO and founder, Frank Dunlap said, “The Universal PHYTM design is optimized for power (5X) lower than UCIe-SP, latency (4x) lower than UCIe-SP, and area (10X) lower than UCIe-SP. We achieve these results by supporting short-reach interconnect currently used in Advanced Packaging design.”
