PSMC launches the 3D AI Accelator technology platform
PSMC has combined the 40nm logic and 25nm DRAM processes, and used wafer stacking technology (Wafer on Wafer) to make a 3D AI accelerator.
The performance is comparable to that of commercially available 7nm systems, but the cost is said to be only a tenth of it, providing a more innovative and competitive AI chip foundry platform for the IC design industry.
In cooperation with the Industrial Technology Research Institute, Smart Memory, and Maxram, the company unveiled the AIM-200 3D AI Accelator technology platform at COMPUTEX 2023. This demonstration chip is based on two 12-inch wafers produced by PSMC's 40nm logic process and 25nm DRAM process, and is integrated by wafer stacking technology, with the data transmission between logic circuits and DRAM to be integrated in one fell swoop. The bandwidth is expanded to 1024 bits. Compared with the existing 32 or 64 bits, it can be said to break through the high memory wall (Memory Wall) that affects the system's computing performance all at once.
According to PSMC, compared with similar AI products, the AIM-200 3D AI Accelator only consumes 1/10 of the power to obtain the same CNN computing efficiency. Although the AI acceleration chip manufactured by the technology platform only uses a 40nm logic process to produce AI Engine and 25nm DRAM, its performance is comparable to similar products produced by a 7nm process, and the demonstration chip operates continuously throughout the day. However, there is still no sign of overheating due to high-speed computing, showing the 'superiority' of the ultra-high transmission bandwidth.
This breakthrough technological innovation has the potential to assist the IC design industry and reduce the cost of AI accelerators by 90%.
