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Cadence wins four 2023 TSMC OIP Partner of the Year Awards

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TSMC presented Cadence with awards for EDA and IP design solutions.

Cadence Design Systems has won four Open Innovation Platform® (OIP) Partner of the Year awards from TSMC for its EDA and IP design solutions. Cadence was presented with awards for the joint development of the N2 and N3P design infrastructure, 3Dblox design prototyping solution, mmWave design solutions and DSP IP. The awards build upon the companies’ long-standing history of collaboration that has delivered many highly innovative SoC and advanced packaging design solutions to the global market.

The awards are based on the following TSMC collaborations:

• N2 and N3P Design Infrastructure: Cadence optimized its complete digital and custom/analog flows for the TSMC N2 and N3E process technologies to help customers achieve power, performance and area (PPA) goals and accelerate innovation. Additionally, Cadence’s AI-powered solutions, Cadence® Cerebrus™ Intelligent Chip Explorer and Virtuoso® Studio, support these nodes, offering customers innovative automation capabilities to make them more efficient.

• Joint Development of 3Dblox Design Prototyping Solution: Design flows based on the Cadence Integrity™ 3D-IC Platform support the TSMC 3Dblox standard for 3D front-end design partitioning in complex systems. The flows include system prototyping flows, which are optimized for all of TSMC’s latest 3DFabric™ offerings, including Integrated Fan-Out (InFO), Chip-on-Wafer-on-Substrate (CoWoS®) and System-on-Integrated-Chips (TSMC-SoIC® ) technologies.

• Joint Development of mmWave Design Solutions: The new Cadence Virtuoso Studio was integrated into the TSMC N16 mmWave RF design reference flow and N6RF design reference flow, and support has been added for the N4P RF design reference flow. In addition, Cadence collaborated with TSMC to optimize the Virtuoso platform for the 79GHz mmWave design reference flow on TSMC’s N16 process.

• DSP IP: Cadence expanded its collaboration with TSMC’s Soft IP9000 team to certify Cadence Tensilica® DSP IP in the TSMC integration flow.

“TSMC works continuously with our OIP design partners to enable technology advancements that make it faster and easier for customers to deliver competitive designs to market, simpler for customers to adopt our solutions,” said Dan Kochpatcharin, head of the Design Infrastructure Management Division at TSMC. “Cadence’s commitment to design excellence is exemplary, and the TSMC OIP Partner of the Year awards are a testament to their dedication to ongoing innovation.”

“By continuing to collaborate closely with TSMC, we’re constantly energized by the innovations our customers bring to life using our technologies,” said Dr. Chin-Chi Teng, senior vice president and general manager of the Digital & Signoff Group at Cadence. “It’s an honor to be recognized with these prestigious TSMC awards, and they are a testament to the work we’ve done to enable our customers to achieve their design and time-to-market goals.”

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