Focus is on efficiency and sustainability
CEA-Leti papers at IEDM 2023, Dec. 9-13, in San Francisco, will present results in multiple fields, including ultimate 3D advances in radio frequency, such as performance improvement at cryogenic temperature.
The institute will present nine papers during the conference this year. Two presentations will highlight a breakthrough in 3D sequential integration and results pushing GaN/Si HEMT closer to GaN/SiC performance at 28 GHz:
“3D Sequential Integration with Si CMOS Stacked on 28nm Industrial FDSOI with Cu-ULK iBEOL Featuring RO and HDR Pixel”, reports the world-first 3D sequential integration of CMOS over CMOS with advanced metal line levels, which brings 3DSI with intermediate BEOL closer to commercialization.
"6.6W/mm 200mm CMOS Compatible AlN/GaN/Si MIS-HEMT with In-Situ SiN Gate Dielectric and Low Temperature Ohmic Contacts" reports development of CMOS compatible 200mm SiN/AlN/GaN MIS-HEMT on silicon substrate that brings GaN/Si high electron mobility transistors (HEMT) closer to GaN/SiC performance at 28 GHz in power density. It also highlights that SiN/AlN/GaN on silicon metal-insulated semiconductor (MIS-HEMT) is a potential candidate for high power Ka-band power amplifiers.
Leti Devices Workshop
“Semiconductor Devices: Moving Towards Efficiency & Sustainability”
Dec. 10 @ 5:30 pm, Nikko Hotel, 222 Mason Street, Third Floor
The workshop will present CEA-Leti experts’ visions for and key results in efficient computing and radiofrequency devices for More than Moore applications.
• RF: "A Cost Effective RF-SOI Drain Extended MOS Transistor Featuring PSAT=19dBm @28GHz & VDD=3V for 5G Power Amplifier Application", by Xavier Garros
o Session 34.2: Wednesday, Dec. 13 @ 9:30 am (Continental 7-9)
• RF crypto: "RF Performance Enhancement of 28nm FD-SOI Transistors Down to Cryogenic Temperature Using Back Biasing", by Quentin Berlingard
o Session 34.3: Wednesday, Dec. 13 @ 9:55 am (Continental 7-9)
• GaN RF: "6.6W/mm 200mm CMOS Compatible AlN/GaN/Si MIS-HEMT with In-Situ SiN Gate Dielectric and Low Temperature Ohmic Contacts", by Erwan Morvan
o Session 38.3: Wednesday, Dec. 13 @ 2:25 pm (Continental 4)
3D Sequential Stacking
• “Ultimate Layer Stacking Technology for High Density Sequential 3D Integration”, a collaborative paper with Ionut Rad of Soitec
o Session 19.5: Tuesday, Dec. 12 @ 4:00 pm (Grand Ballroom A)
• “3D Sequential Integration with Si CMOS Stacked on 28nm Industrial FDSOI with Cu-ULK iBEOL Featuring RO and HDR Pixel”, by Perrine Batude
o Session 29.3: Wednesday, Dec. 13 @ 9:55 am (Grand Ballroom B)
Emerging Device and Compute Technology (EDT)
• “Designing Networks of Resistively-Coupled Stochastic Magnetic Tunnel Junctions for Energy-Based Optimum Search”, by Kamal Danouchi
o Session 22.3: Tuesday, Dec. 12 @ 3:10 (Continental 5)
• Hybrid FeRAM/RRAM Synaptic Circuit Enabling On-Chip Inference and Learning at the Edge”, by Michele Martemucci (LIST)
o Session 23:3: Tuesday, Dec. 12 @ 3:10 (Continental 6)
• “Bayesian In-Memory Computing with Resistive Memories”, a collaborative paper with Damien Querlioz of CNRS-C2N
o Session 12:3: Tuesday, Dec. 12 @ 9:55 am (Continental 1-3)
• “Tunnel and Capacitive Coupling Optimization in FDSOI Spin-Qubit Devices”, by H. Niebojewski and B. Bertrand
o Session 22:6: Tuesday, Dec. 12 @ 4:25 pm (Continental 5)