Effective hermetic sealing for next-generation microelectronic packaging

A perfectly sealed electronic package can fulfill its intended function without disruption, error or a significant reduction in performance for decades. However, design and field engineers can only achieve this level of performance by applying the right materials and sealants, and employing the correct tools, equipment and process steps to build semiconductor-driven electronic packages for the next generation. The confidence engendered by a well-sealed package inevitably leads to the development of better chips with more features.

BY RAMESH KOTHANDAPANI, TECHNICAL DIRECTOR, MICROELECTRONIC PACKAGING, MATERION CORPORATION

HERMETIC SEALING is an important process for packaging semiconductor chips. The word “hermetic,” in this case, suggests leak-safe sealing. A semiconductor chip goes through several process steps, starting as a wafer before being cut into individual chips and eventually ending up in a discrete package. Such chips are strongly bonded to die pads with a die-attach epoxy or eutectic solders. They are then electrically connected to the ceramic package bond pads with very fine wires.

The ceramic package – in effect a “chip carrier” – is generally multi-layered with electrical feedthroughs within its ceramic body. These layers are internally connected to the bottom or sides of the package to be mounted onto printed circuit boards along with other electrical components. An array of packages is available for chip bonding, including leaded chip carrier (LCC); ceramic, quad, flatpack (CQFP), and quad-flat package (QFP), among others.

The ceramic package is seam-sealed with two electrodes running parallel to melt the lid and seal it to the ceramic or metal package.

The ceramic package with seal ring and wire and die-bond pads.

The ceramic package with chip attachment.

Ceramic package with seal ring dimensions.

The ceramic package containing the chip with wire bonds must eventually be hermetically sealed to prevent the entry of contaminants such as moisture or loose particles.

The hermetic sealing process is vital to determining the viability of the assembly in operation. Illustration 1 shows the semiconductor chip and its hundreds of very fine wire bonds. These chips range in size from a few millimeters to tens of millimeters. Smaller chips may have fewer wire bonds, while larger chips can have hundreds. These bonds are thinner than a human hair, with diameters as small as 0.0007 inch (17.78 microns).

Design guidelines for package lid and solder.

Illustration 7. Gold-Tin phase diagram.

Exploded view of ceramic package, solder frame and plated metal lid.

Discrete chips contain micro-electromechanical systems (MEMS) with super-fine gears, clocks and moving actuators that cannot be seen with the naked eye. Any particles that deposit on these chips are likely to interfere with their performance. Equally, with the bonded fine wires so close to each other, conductive particles or moisture between the wires could cause a malfunction. This makes proper hermetic sealing of the assembled packages even more important.

Before focusing on the sealing process, it’s important to know about materials which are used for sealings, its limitations, the design guidelines, storage, and handling processes.

Cross section image of four layers plated sequentially with nickel and gold.

There are, for example, several types of ceramic packages:

• Surface mount ceramic packages
• Ceramic pin grid array packages
• Ceramic quad flat packages
• Ceramic hybrid packages
• Fiber-optic communication packages
• The bonding materials or solders
• The components which have to be attached to the package such as dies, die attach materials, wires and etc.

Depending on the level of hermeticity required, packages undergo one or two sealing processes: seam-sealed with a metal lid, or solder-sealed with a plated metal lid.

Nickel migration process.

Frame lid assembly.