Effective hermetic sealing for next-generation microelectronic packaging

A perfectly sealed electronic package can fulfill its intended function without disruption, error or a significant reduction in performance for decades. However, design and field engineers can only achieve this level of performance by applying the right materials and sealants, and employing the correct tools, equipment and process steps to build semiconductor-driven electronic packages for the next generation. The confidence engendered by a well-sealed package inevitably leads to the development of better chips with more features.

BY RAMESH KOTHANDAPANI, TECHNICAL DIRECTOR, MICROELECTRONIC PACKAGING, MATERION CORPORATION

HERMETIC SEALING is an important process for packaging semiconductor chips. The word “hermetic,” in this case, suggests leak-safe sealing. A semiconductor chip goes through several process steps, starting as a wafer before being cut into individual chips and eventually ending up in a discrete package. Such chips are strongly bonded to die pads with a die-attach epoxy or eutectic solders. They are then electrically connected to the ceramic package bond pads with very fine wires.

The ceramic package – in effect a “chip carrier” – is generally multi-layered with electrical feedthroughs within its ceramic body. These layers are internally connected to the bottom or sides of the package to be mounted onto printed circuit boards along with other electrical components. An array of packages is available for chip bonding, including leaded chip carrier (LCC); ceramic, quad, flatpack (CQFP), and quad-flat package (QFP), among others.

The ceramic package is seam-sealed with two electrodes running parallel to melt the lid and seal it to the ceramic or metal package.

The ceramic package with seal ring and wire and die-bond pads.