Loading...
News Article

Adeia wins ECTC Award for paper on “Fine Pitch Die-to-Wafer Hybrid Bonding”

News

Adeia Inc., a leading research and development and intellectual property licensing company known for bringing innovations in the semiconductor and media technology sectors to market, was awarded Best Session Paper at the 2024 Electronic Components and Technology Conference (ECTC) held in Denver, Colorado on May 28-31, 2024.

“It achieves this by facilitating higher interconnect density than alternatives like micro-bumps, thereby improving bandwidth and lowering latency. Higher density of interconnections between the memory die and logic chip improves performance and efficiency while offering better thermal connectivity.”

Dr. Thomas Workman, senior principal engineer for Adeia and author of the paper, received the award for “Fine Pitch Die-to-Wafer Hybrid Bonding,” which explores the range of parameters associated with implementing hybrid bonding technology in high-volume manufacturing processes.

“As adoption of hybrid bonding accelerates, there is rising demand for practical information and guidance on implementing the technology in high volume manufacturing. This paper provides a detailed pathway for manufacturers to understand the parameters, limitations and yield considerations of hybrid bonding, ultimately enabling industry leaders to successfully implement the technology in their own processes,” said Dr. Workman.

Hybrid bonding technology in advanced 2.5 and 3D packaging has rapidly gained traction in the semiconductor industry to enhance performance and scalability. Advanced packaging architectures integrate multiple semiconductor components into a single package or module to create functional systems. Within the package or module, a chip-to-chip interconnect is formed with hybrid bonding to deliver the highest bandwidth with low latency.

Hybrid bonding represents a significant advancement in semiconductor technology, particularly in terms of performance per watt.

“By enabling faster processing within established thermal limits, hybrid bonding enhances efficiency and reduces energy consumption,” explained Dr. Workman. “It achieves this by facilitating higher interconnect density than alternatives like micro-bumps, thereby improving bandwidth and lowering latency. Higher density of interconnections between the memory die and logic chip improves performance and efficiency while offering better thermal connectivity.”

Looking ahead, Dr. Workman stated that hybrid bonding is gaining increasing traction in high-volume manufacturing applications. Interest and activity in hybrid bonding are expected to grow as progress is made in shrinking the pitch to a submicron level.

“This would allow hybrid bonding to be a solution for an even wider range of applications. The next step is demonstrating how hybrid bonding can be implemented with standard equipment and processes. This will expand the practical opportunities to leverage the full benefits of this technology,” he concludes.

With over 20 years of experience in process and equipment engineering, Dr. Workman has successfully launched and managed fabrication and assembly lines for semiconductors, photonics, solar cells and nanotechnology. He is known for his excellent problem-solving skills as well has his deep knowledge of materials and manufacturing systems.

Silicon photonics: accelerating growth in the race for high-speed optical interconnects
CCD-in-CMOS technology enables ultra-fast burst mode imaging
2025 6G A look forward
Critical Manufacturing climbs Deloitte’s Technology Fast 50
Semiconductors: The most important thing you probably know the least about
Imec and partners unveil SWIR sensor with lead-free quantum dot photodiodes
Lattice introduces small and mid-range FPGA offerings
SEMI and SMT inspection solutions at NEPCON Japan 2025
Nordic Semiconductor and Kigen demonstrate Remote SIM Provisioning for Massive IoT
Spirent collaborates with Siemens
Quobly forges strategic collaboration with STMicroelectronics
New standards in pressure measurement systems for the semiconductor industry
IBM delivers optics breakthrough
Semiconductor equipment sales to reach $139 Billion in 2026
Marvell introduces 1.6 Tbps LPO Chipset
ACM research strengthens Atomic Layer Deposition portfolio
CEA-Leti demonstrates embedded FeRAM platform compatible with 22nm FD-SOI node
Lattice introduces small and mid-range FPGA offerings
Solace unlocks full potential of event-driven integration
Advantest to showcase latest test solutions at SEMICON Japan 2024
CEA-Leti device integrates light sensing and modulation
Nordic launches Thingy:91 X prototyping platform for cellular IoT and Wi-Fi locationing
Imec achieves seamless InP Chiplet integration on 300mm RF Silicon Interposer
High-precision SMU
Powering India’s energy future
China’s Nvidia probe puts global investors ‘on notice’
POET Technologies appoints new director
Imec demonstrates core building blocks of a scalable, CMOS-fab compatible superconducting digital technology
Imec proposes double-row CFET for the A7 technology node
ULVAC launches new deposition system
Beebolt and SEMI Announce Strategic Partnership to Drive Supplier Resilience and Agility
esmo group introduces Automated Final Test Manipulator
×
Search the news archive

To close this popup you can press escape or click the close icon.
Logo
x
Logo
×
Register - Step 1

You may choose to subscribe to the Silicon Semiconductor Magazine, the Silicon Semiconductor Newsletter, or both. You may also request additional information if required, before submitting your application.


Please subscribe me to:

 

You chose the industry type of "Other"

Please enter the industry that you work in:
Please enter the industry that you work in: