Loading...
News Article

Sivers Semiconductors receives $5.6 million CHIPS Act funding

News

The company will be working with partners to accelerate critical chip technologies from lab to fab

Sivers Semiconductors has announced that it has received first-year funding of $5.6 million from the Northeast Microelectronics Coalition (NEMC) Hub through the US CHIPS and Science Act.

The funding comes under the Microelectronics Commons programme, executed through the Naval Surface Warfare Center Crane Division and the National Security Technology Accelerator (NSTXL).

The award funds collaboration between the company and partners BAE Systems, MIT Lincoln Laboratory, and Columbia University to accelerate domestic prototyping and expand the nation’s global leadership in microelectronics. This is one of six projects awarded to the NEMC Hub, led by Massachusetts Technology Collaborative (MassTech), under the Microelectronics Commons Program.

According to Sivers Semiconductors, it will lead the Electronic Warfare Technology Program, focusing on self-interference cancellation circuits that enable full-duplex arrays that can transmit and receive at the same time and the same frequency. Such simultaneous transmit and receive (STAR) arrays enable new multi-function capabilities for electronic warfare systems, such as joint radar and communications. They also have dual-use commercial applications, specifically in range-extending repeaters.

The primary challenge with full-duplex or simultaneous-transmit-and-receive operation is the self-interference from the transmitter to the receiver, which can be a billion to a trillion times more powerful than the desired signal to be received. This necessitates highly precise self-interference cancellation circuitry that can cancel the transmitter leakage with a one-part-per-billion/trillion accuracy.

Furthermore, accomplishing this self-interference cancellation in large arrays, such as those used in electronic warfare systems as well as 5G millimetre-wave and FR3, is yet another challenge. Sivers Semiconductors says that this programme, which is renewable across three years, will transition technology developed at Columbia University, BAE Systems and MIT Lincoln Laboratory to product-grade implementations and deployment readiness.

“This initiative opens new applications and verticals in the defence sector for Sivers,” said Vickram Vathulya, CEO of Sivers Semiconductors. “Our collaboration with industry leading partners such as BAE, one of the two largest suppliers of electronic warfare technology within the US defence industrial base, will accelerate our go-to-market strategy in electronic warfare.”

Carolyn Kirk, CEO of MassTech, said: “This award highlights the ingenuity and expertise that exists across the Northeast when it comes to microelectronics and semiconductors. The technology development and transition partnerships being fostered by the NEMC Hub will have an enduring impact on our national and economic security.”

Harish Krishnaswamy, managing director, Wireless Division at Sivers Semiconductors, added: “It is exciting to explore new applications for our expertise and technology in beamforming and interference-tolerant chip design. Our collaboration with a leading defence prime, a leading academic institution and the top federally-funded R&D centre ensures that our team has all the skills and resources to be successful.”

NEMC Hub Director Mark Halfman said: “This award is a testament to the hard work, collaboration, and leadership the NEMC Hub and its members have demonstrated during the first year of the Microelectronics Commons. We have a tremendous opportunity to grow microelectronics lab-to-fab capabilities and spur the growth of game-changing technologies.”

esmo group launches Apollo Quad Handler
Mycronic receives order for two SLX mask writers
Tenstorrent expands deployment of Arteris’ Network-on-Chip IP
Wet etch and clean solution with integrated metrology
James Culp of GlobalFoundries joins Si2 Board
Infineon presents new ASIL-D-compliant 3-phase gate driver IC
JST names Dr. Ismail Kashkoush as Chief Technology Officer
DuPont earns Best Partner Award for Innovation from Samsung Electronics
Advantest to showcase latest semiconductor test solutions
Infineon introduces DEEPCRAFT brand for Edge AI software solutions
Ohio State University selects Veeco system
Global Wafer Fab Equipment revenue poised to surge
New educational initiative for the German chip industry
ZEISS launches Crossbeam 550 Samplefab FIB-SEM
Critical Manufacturing brings highly advanced MES solution to SEMICON Europa
Infineon at electronica 2024: Solutions for decarbonisation and digitalisation
Infineon unveils "world’s thinnest" silicon power wafer
Sunlit Chemical expands global reach with US facility opening in Phoenix
Semiconductor patent applications up 22% globally to 81,000 a year
Promoting collaboration and novel IC design technologies
EV Group announces board expansion In light of unabated growth
MIT team takes a major step toward fully 3D-printed active electronics
TSMC recognises Ansys
Quantum foundry nears completion
Global silicon wafer shipments to remain soft in 2024
DELO introduces UV-approach for fan-out wafer-level packaging
New 10-point guide to humidity control in cleanrooms
High memory bandwidth in the spotlight
Improved materials for microchip interconnections
SEMICON Europa 2024 to explore innovations in Advanced Packaging and Fab Management
SEMIExpo Vietnam 2024 heralds Vietnam’s position as 'dynamic new player'
Next Gen 3D X-Ray Inspection for Advanced Packaging: To see better. Faster. More.
×
Search the news archive

To close this popup you can press escape or click the close icon.
Logo
x
Logo
×
Register - Step 1

You may choose to subscribe to the Silicon Semiconductor Magazine, the Silicon Semiconductor Newsletter, or both. You may also request additional information if required, before submitting your application.


Please subscribe me to:

 

You chose the industry type of "Other"

Please enter the industry that you work in:
Please enter the industry that you work in: