Loading...
News Article

Infineon unveils "world’s thinnest" silicon power wafer

News

Pushes technical boundaries and improves energy efficiency.

After announcing the world’s first 300-millimeter gallium nitride (GaN) power wafer and opening the world’s largest 200-millimeter silicon carbide (SiC) power fab in Kulim, Malaysia, Infineon Technologies has unveiled the next milestone in semiconductor manufacturing technology. Infineon has reached a breakthrough in handling and processing the thinnest silicon power wafers ever manufactured, with a thickness of only 20 micrometers and a diameter of 300 millimeters, in a high-scale semiconductor fab. The ultra-thin silicon wafers are only a quarter as thick as a human hair and half as thick as current state-of-the-art wafers of 40-60 micrometers.

“The world's thinnest silicon wafer is proof of our dedication to deliver outstanding customer value by pushing the technical boundaries of power semiconductor technology,” said Jochen Hanebeck, CEO at Infineon Technologies. “Infineon’s breakthrough in ultra-thin wafer technology marks a significant step forward in energy-efficient power solutions and helps us leverage the full potential of the global trends decarbonization and digitalization. With this technological masterpiece, we are solidifying our position as the industry’s innovation leader by mastering all three relevant semiconductor materials: Si, SiC and GaN.”

This innovation will significantly help increase energy efficiency, power density and reliability in power conversion solutions for applications in AI data centers as well as consumer, motor control and computing applications. Halving the thickness of a wafer reduces the wafer’s substrate resistance by 50 percent, reducing power loss by more than 15 percent in power systems, compared to solutions based on conventional silicon wafers. For high-end AI server applications, where growing energy demand is driven by higher current levels, this is particularly important in power conversion: Here voltages have to be reduced from 230 V to a processor voltage below 1.8 V. The ultra-thin wafer technology boosts the vertical power delivery design, which is based on vertical Trench MOSFET technology and allows a very close connection to the AI chip processor, thus reducing power loss and enhancing overall efficiency.

“The new ultra-thin wafer technology drives our ambition to power different AI server configurations from grid to core in the most energy efficient way,” said Adam White, Division President Power & Sensor Systems at Infineon. “As energy demand for AI data centers is rising significantly, energy efficiency gains more and more importance. For Infineon, this is a fast-growing business opportunity. With mid-double-digit growth rates, we expect our AI business to reach one billion euros within the next two years.”

To overcome the technical hurdles in reducing wafer thickness to the order of 20 micrometers, Infineon engineers had to establish an innovative and unique wafer grinding approach, since the metal stack that holds the chip on the wafer is thicker than 20 micrometers. This significantly influences handling and processing the backside of the thin wafer. Additionally, technical and production-related challenges like wafer bow and wafer separation have a major impact on the backend assembly processes ensuring the stability and first-class robustness of the wafers. The 20-micrometer thin wafer process builds on Infineon’s existing manufacturing expertise and ensures that the new technology can be seamlessly integrated into existing high-volume Si production lines without incurring additional manufacturing complexity, thus guaranteeing the highest possible yield and supply security.

The technology has been qualified and applied in Infineon’s Integrated Smart Power Stages (DC-DC converter) which have already been delivered to first customers. It underlines the company’s innovation leadership in semiconductor manufacturing as the holder of a strong patent portfolio related to the 20-micrometer wafer technology. With the current ramp up of the ultra-thin wafer technology Infineon expects a replacement of the existing conventional wafer technology for low voltage power converters within the next three to four years. This breakthrough is bolstering Infineon’s unique position in the market with the broadest product and technology portfolio including silicon, silicon carbide and gallium nitride-based devices which are key enablers of decarbonization and digitalization.

Infineon will present the first ultra-thin silicon wafer publicly at electronica 2024 from 12 to 15 November in Munich (Hall C3, Stand 502).

Silicon photonics: accelerating growth in the race for high-speed optical interconnects
CCD-in-CMOS technology enables ultra-fast burst mode imaging
2025 6G A look forward
Critical Manufacturing climbs Deloitte’s Technology Fast 50
Semiconductors: The most important thing you probably know the least about
Imec and partners unveil SWIR sensor with lead-free quantum dot photodiodes
Lattice introduces small and mid-range FPGA offerings
SEMI and SMT inspection solutions at NEPCON Japan 2025
Nordic Semiconductor and Kigen demonstrate Remote SIM Provisioning for Massive IoT
Spirent collaborates with Siemens
Quobly forges strategic collaboration with STMicroelectronics
New standards in pressure measurement systems for the semiconductor industry
IBM delivers optics breakthrough
Semiconductor equipment sales to reach $139 Billion in 2026
Marvell introduces 1.6 Tbps LPO Chipset
ACM research strengthens Atomic Layer Deposition portfolio
CEA-Leti demonstrates embedded FeRAM platform compatible with 22nm FD-SOI node
Lattice introduces small and mid-range FPGA offerings
Solace unlocks full potential of event-driven integration
Advantest to showcase latest test solutions at SEMICON Japan 2024
CEA-Leti device integrates light sensing and modulation
Nordic launches Thingy:91 X prototyping platform for cellular IoT and Wi-Fi locationing
Imec achieves seamless InP Chiplet integration on 300mm RF Silicon Interposer
High-precision SMU
Powering India’s energy future
China’s Nvidia probe puts global investors ‘on notice’
POET Technologies appoints new director
Imec demonstrates core building blocks of a scalable, CMOS-fab compatible superconducting digital technology
Imec proposes double-row CFET for the A7 technology node
ULVAC launches new deposition system
Beebolt and SEMI Announce Strategic Partnership to Drive Supplier Resilience and Agility
esmo group introduces Automated Final Test Manipulator
×
Search the news archive

To close this popup you can press escape or click the close icon.
Logo
x
Logo
×
Register - Step 1

You may choose to subscribe to the Silicon Semiconductor Magazine, the Silicon Semiconductor Newsletter, or both. You may also request additional information if required, before submitting your application.


Please subscribe me to:

 

You chose the industry type of "Other"

Please enter the industry that you work in:
Please enter the industry that you work in: