Arteris and MIPS partner
Pre-verified reference platform supports the acceleration of RISC-V-based SoC designs with mutual customers.
Arteris and MIPS are partnering to provide a pre-verified reference platform to support mutual customers. The creation of this pre-verified reference platform is designed to shorten development cycles and reduce risk for RISC-V-based chip designs for automotive, enterprise computing and edge AI applications.
MIPS develops high-performance RISC-V CPU IP for AI, automotive and general-purpose computing. By pre-integrating Arteris network-on-chip IP, including Ncore cache coherent NoC IP and FlexNoC IP with the MIPS P8700 processor core clusters, the two IP providers demonstrate the interoperability and performance of the joint solution. Customers can confidently leverage the silicon-proven solution demonstrated by a pre-verified reference platform supported by both Arteris and MIPS.
Arteris network-on-chip IP technology provides on-die or on-chip connectivity, supporting both homogeneous and heterogeneous architectures, and can simultaneously handle AMBA ACE and CHI protocols. This unique flexibility and configurability facilitate quick development and optimized RISC-V-based SoCs.
“We are pleased to work with Arteris, whose Ncore and FlexNoC IPs have been deployed by our customers. This partnership allows us to deliver a pre-verified solution that mitigates risk and accelerates our customers' design time,” said Drew Barbier, VP of product at MIPS. “Many of our shared customers have successfully deployed our technologies, and this partnership enables us to better meet the demands of advanced automotive and general-purpose applications.”
“We are excited to support MIPS in the development of their next-generation RISC-V processor cores and support our mutual customers with this pre-verified solution,” said Michal Siwinski, CMO of Arteris. “This partnership underscores our commitment to support the broader ecosystem by delivering RISC-V ready NoC interconnects that not only enhance performance and reduce SoC power, but also improve scalability for future electronic innovations.”
