Synopsys expands Hardware-Assisted Verification Portfolio
New Synopsys Emulation and Prototyping Ready (EP-Ready) Hardware enables configuration for emulation and prototyping use-cases within and across multiple projects on a single hardware platform.
Synopsys is expanding its industry-leading hardware-assisted verification (HAV) portfolio with new HAPS® prototyping and ZeBu® emulation systems using the latest AMD Versal™ Premium VP1902 adaptive SoC. The next generation HAPS-200 prototyping and ZeBu-200 emulation systems deliver improved runtime performance, better compile time and improved debug productivity. They are built on new Synopsys Emulation and Prototyping (EP-Ready) Hardware that optimizes customer return on investment by enabling emulation and prototyping use cases via reconfiguration and optimized software. ZeBu Server 5 is enhanced to deliver industry-leading scalability beyond 60 billion gates (BG) to address the escalating hardware and software complexity in SoC and multi-die designs. It continues to offer industry-best density to optimize data center space utilization.
"With the industry approaching 100s of billions of gates per chip and 100s of millions of lines of software code in SoC and multi-die solutions, verification of advanced designs poses never-before seen challenges," said Ravi Subramanian, chief product management officer, Synopsys. "Continuing our strong partnership with AMD, our new systems deliver the highest HAV performance while offering the ultimate flexibility between prototyping and emulation use. Industry leaders are adopting Synopsys EP-Ready Hardware platforms for silicon to system verification and validation."
HAPS-200 Prototyping and ZeBu-200 Emulation Systems Offer 2X Performance Increase and Advanced Debug Capabilities
The Synopsys HAPS-200 prototyping system offers industry-leading runtime performance and faster compile with 4X improved debug performance over HAPS-100. It leverages the existing HAPS-100 ecosystem and supports mixed HAPS-200/100 system setups scalable from single FPGA to multi-rack setups with capacity of up to 10.8 BG.
While extending design capacity to up to 15.4 BG, the Synopsys ZeBu-200 emulation system also offers up to 2X higher runtime performance compared to the previous generation ZeBu EP2 with faster compile time, reducing turnaround time and enhancing development productivity. It features up to 8X better debug bandwidth, offering 200 GB debug trace memory per module and improved job scheduling and relocation.
"With the increasing market requirements for handling large AI computational data sets driving the need for enormous GPU and CPU computational power, the development time for NVIDIA's next generation AI systems have become highly compressed to a yearly release cycle, necessitating best-in-class prototyping solutions," said Narendra Konda, vice president, Hardware Engineering at NVIDIA. "Synopsys HAPS-200 offers the fastest prototyping speed in the industry. The 50 MHz performance we have been able to achieve with HAPS-200 has been key to boosting productivity of our software development teams. We are looking forward to scaling our HAPS-200 deployment to take full advantage for our software development teams."
Synopsys EP-Ready Hardware Platform Provides Highest ROI
The HAPS-200 and ZeBu-200 systems are built on the Synopsys EP-Ready Hardware platform to optimize ROI for customers and eliminate the need to decide the required balance of emulation and prototyping hardware upfront. The EP-Ready Hardware platform supports cables and hubs for direct and scalable connectivity. Users can leverage the broad portfolio of solutions for leading interface protocols through the transactors and speed adaptors.
"The future of emulation and prototyping demands unprecedented performance, adaptability, and scalability," said Salil Raje, senior vice president and general manager, Adaptive and Embedded Computing Group at AMD. "By integrating the AMD Versal Premium VP1902 adaptive SoC, with its industry-leading capacity*, performance, and debug capabilities, into Synopsys' EP-Ready platforms we're not only improving performance metrics, we're also transforming how engineering teams can validate and optimize their most ambitious new ASIC and SoC designs. Our longstanding partnership with Synopsys empowers design teams to tackle their most complex verification challenges, from AI/ML workloads to multi-die architectures, while dramatically accelerating time to market."
"Synopsys is a key member of Arm Total Design, bringing critical tools and the advanced HAV capabilities to quickly and reliably validate solutions built on Arm Compute Subsystems (CSS)," said Kevork Kechichian, executive vice president, Solutions Engineering, Arm. "The new ZeBu-200 and HAPS-200 hardware platforms will also assist our mutual customers in integrating Arm CSS into their designs with improved turnaround times to meet the demanding requirements for complex data center infrastructure and automotive systems."
Increasing Scalability for Multi-Die Designs and Accelerating Software Bring-Up
Already in use with customers leveraging HAPS prototyping, Synopsys extends its methodology of "Modular HAV" to ZeBu Server 5, growing its industry leading scalability beyond 60 BG to meet the industry's growing emulation capacity needs, to significantly reduce compile time and compute resources, and to enable emulation for the largest multi-die designs. The Modular HAV methodology utilizes interface protocol solutions that leverage Synopsys' broad portfolio of complete, silicon-proven interface IP.
In addition, Synopsys hybrid technology combines the use of a virtual model running on a host server connected to an HAV system. Synopsys Virtualizer™ now supports multi-threading technology. This advanced technology significantly accelerates software bring-up processes, such as enabling a full Android boot in less than 10 minutes.
