AMD achieves first TSMC N2 product silicon milestone
Next-generation AMD EPYC CPU, codenamed “Venice,” is the first HPC product to be brought up on TSMC’s next-generation N2 node.
AMD says that its next-generation AMD EPYC™ processor, codenamed “Venice,” is the first HPC product in the industry to be taped out and brought up on the TSMC advanced 2nm (N2) process technology. This highlights the strength of AMD and TSMC semiconductor manufacturing partnership to co-optimize new design architectures with leading-edge process technology. It also marks a major step forward in the execution of the AMD data center CPU roadmap, with “Venice” on track to launch next year. AMD also announced the successful bring up and validation of its 5th Gen AMD EPYC™ CPU products at TSMC’s new fabrication facility in Arizona, underscoring its commitment to U.S. manufacturing.
“TSMC has been a key partner for many years and our deep collaboration with their R&D and manufacturing teams has enabled AMD to consistently deliver leadership products that push the limits of high-performance computing,” said Dr. Lisa Su, chair and CEO, AMD. “Being a lead HPC customer for TSMC’s N2 process and for TSMC Arizona Fab 21 are great examples of how we are working closely together to drive innovation and deliver the advanced technologies that will power the future of computing.”
“We are proud to have AMD be a lead HPC customer for our advanced 2nm (N2) process technology and TSMC Arizona fab,” said TSMC Chairman and CEO Dr. C.C. Wei. “By working together, we are driving significant technology scaling resulting in better performance, power efficiency and yields for high-performance silicon. We look forward to continuing to work closely with AMD to enable the next era of computing.”
