SUSS MicroTec announced new capabilities for cost-effective 1X full-field lithography (1XFFL) with a package of four new technologies. Known collectively as SupraYield, the enhancements provide a high-performance 1XFFL solution for advanced thick-resist applications, such as wafer-level packaging, MEMS and optoelectronics.
Micronas introduced what it calls "ActivePackage" – aimed at ridding a headache car manufacturers worldwide have shared for many years. During the life cycle of a car, several of the original integrated circuits (IC) that are designed in when the car is launched become obsolete - forcing car manufacturers to carry out expensive redesigns.
Surface Technology Systems (STS) unveiled its Pro family of plasma etch and deposition tools aimed at the transition from the "technology driven" era of micro-electro-mechanical system (MEMS) technology into volume production.
Oxford University is looking for partners to help it commercialise a simple treatment technique for purifying crude samples of single and multi-walled carbon nanotubes (SW and MW-CNTs) to produce a clean, well dispersed product currently containing greater than 90% semiconducting CNTs.
X-FAB Semiconductor Foundries announced an expansion of its MEMS product line to include surface micromachining technology for absolute pressure sensors. The technology enables integration of absolute pressure sensors with X-FAB's CMOS technologies. The sensors can also be implemented as discrete components.
The new Pro generation of equipment platforms from Surface Technology
Systems drives down the cost-per-die for single wafer plasma processes
across a wide range of applications. The platforms are available with the
full compliment of STS' well-established plasma etch and deposition sources
in loadlocked or cluster format.
The Pro range delivers a compact footprint, with the latest generation of
PLC-based control system providing enhanced communications, reliability and
functionality coupled with faster and simpler maintenance operations. An
improved user interface, conforming to SEMI E95 further improves the
intuitive look and feel of the systems.
For MEMS silicon micromachining applications etch rates of up to 20
microns/min are available, and for optical devices, sidewall smoothness of
20nm are reproducibly demonstrated. A new showerhead design for PECVD
processes delivers exceptional deposition rates and uniformity. For
example, for optical waveguide applications, 7800 angstroms/min for BPSG
clad and 4500 angstroms/min for Ge-doped silica core layers. Greater
yields, reduced cleaning and minimal consumable parts combine to reduce
further the cost-per-die for both etch and deposition processes.
For further information, click
http://www.stsystems.com/latest_news/Pro_news5.html, or Email:
Surface Technology Systems plc,
tel. +44 1633 652400
A NUMBER OF YEARS THERE HAS BEEN INDUSTRY DISCUSSION ON THE MERITS OF
SINGLE WAFER PROCESSING AS OPPOSED TO BATCH WAFER PROCESSING. ALTHOUGH
THE BATTLE CONTINUES EARLY ANALYSIS SUGGEST SINGLE WAFER PROCESSING MAY
BE FASTER OVERALL. HEINZ OYRER, DIRECTOR OF STRATEGIC MARKETING AT SEZ
DISCUSSES THE BENEFITS OF THE NEW RANGE OF SINGLE WAFER CLEANERS TO COME
FROM SEZ AND HOW THEY WILL UP THE ANTE FOR SINGLE WAFER PROCESSING.
Technology Innovations LLC and Innovation On Demand Inc. have been issued a US patent for a "Wireless Technique for Microactivation" (No.6,588,208). The patent covers microactuators that can be operated wirelessly by focused beams of energy, enabling the devices to control objects in the 100nm range.
DEK and PacTech USA have formed a solder bump technology partnership. By combining PacTech’s electroless under bump metallisation (UBM) processing with DEK’s mass imaging systems to create solder bumps, users can implement a wafer-level, SMT-compatible flip chip assembly process.
Toshiba has developed and verified the operability of a memory cell technology for embedded DRAM system LSIs on silicon-on-insulator (SOI) wafers, claimed as a world first. Toshiba aims to apply the new technology to mass production of system LSIs for broadband network applications in 2006. Toshiba has experimentally fabricated a 96kbit cell array. Full details of the new technology were presented at the VLSI Symposium in Kyoto, Japan.