Imec produces the first fully self-aligned, two-metal-level, semi-damascene module

Semi-damascene integration is an attractive, cost-effective approach to extend interconnect process flows below 20nm metal pitch. Imec proposed its approach five years ago, and now confirms the first experimental demonstration of a functional, two-metal-level semi-damascene module at 18nm pitch.

BY GAYLE MURDOCH, TECHNICAL STAFF PRINCIPAL MEMBER AND ZSOLT TOKEI, IMEC FELLOW AND PROGRAM DIRECTOR FOR NANO-INTERCONNECTS

FOR MORE THAN 20 YEARS, copper (Cu) dual-damascene has been the workhorse process flow for building reliable interconnects. But when dimensional scaling continues and metal pitches become as tight as 20 nm and below, the
back-end-of-line (BEOL) increasingly suffers from RC delay, which is the result of a dramatically growing resistance-capacitance (RC) product. This has forced the interconnect community to start looking for alternative integration schemes and metals, with better figures of merit at tight metal pitches.

In this article, imec researchers Gayle Murdoch and Zsolt Tokei highlight the importance of via self-alignment at tight pitch, explain and demonstrate the key technical parameters of the module including via and line resistance as well as reliability. The results were presented at the 2022 IEEE VLSI Symposium on Technology and Circuits (VLSI 2022).

Figure 1: Imec’s semi-damascene flow: a) Ru etch (formation of the bottom local interconnect line (Mx)); b) gap fill; c) via etch; and d) via fill and top line (Mx+1) formation (as presented at VLSI 2022).

About five years ago, imec initially proposed semi-damascene as a viable alternative to Cu dual-damascene for integrating the most critical local (Mx) interconnect layers of the 1nm (and beyond) technology nodes.

Unlike dual-damascene, semi-damascene integration relies on the direct patterning of the interconnect metal for making the lines (referred to as subtractive metallization). No chemical mechanical polishing (CMP) of the metal is needed for completing the process flow.

The vias that connect subsequent interconnect layers are patterned in single-damascene fashion, then filled with metal and overfilled - meaning that the metal deposition continues until a layer of metal is formed over the dielectric. This layer of metal is then masked and etched to form the second interconnect layer with orthogonal lines.

After metal patterning, the gaps between the lines can be filled with a dielectric or can be used to form (partial) airgaps at the local layers. Note that in a semi-damascene flow, two layers (via and top metal) are formed in one-go, just like for conventional dual-damascene. This makes it effectively cost competitive, when benchmarked with dual-damascene (see figure 2).

Figure 2: Comparison of semi-damascene and dual-damascene cost at 18 nm metal pitch.

Benefits of a semi-damascene integration flow
Semi-damascene promises several advantages over Cu dual-damascene at tight metal pitches according to Zsolt Tokei, imec fellow and program director for nano-interconnects. “Firstly, it allows for higher line aspect ratios while keeping capacitance under control – promising an overall RC benefit. Secondly, the absence of a metal CMP step leads to a more simplified and cost-effective integration scheme.

Finally, semi-damascene integration requires a barrierless, patternable metal such as tungsten (W), molybdenum (Mo) or ruthenium (Ru). By using metals that, unlike Cu, do not require a metal barrier, the precious conductive area can be fully utilized by the interconnect metal itself. This ensures competitive via resistance at scaled dimensions.”

Besides the benefits there are of course numerous challenges to tackle before such a scheme would get industrial acceptance. One step in that direction is the actual demonstration of a two-metal-level scheme. While the benefits have so far only been showed through simulation and modelling, imec has for the first time provided experimental evidence with a two-metal-level semi-damascene module.

The fully self-aligned via – a critical building block
At metal pitches as tight as 20 nm, controlled via landing on top of the narrow lines is key to the successful operation of the semi-damascene integration module. When the via and the lines (at both via top and bottom) are not properly aligned, there is a risk of leakage between the via and an adjacent line. These leakage paths are the result of a too large overlay error induced by conventional patterning of the small via holes.

Gayle Murdoch, principle member of technical staff at imec said, “Finding a way for making functional, fully self-aligned vias has been a holy grail of the semi-damascene process. We achieved this milestone through intense collaboration between the integration, lithography, etch and cleaning groups at imec. With our fully-self aligned integration scheme, we were able to compensate for overlay errors up to 5 nm – a key achievement.”

Bottom self-alignment was ensured by the selective removal of silicon nitride after gap fill, allowing the via to form on the confines of the lower metal line. The self-alignment towards the top metal layer (Ru) was achieved by the Ru over-etch step, applied after via overfill and Ru patterning.