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Extending The Era Of Moore's Law Through Lower Cost Patterning

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Peng Zheng1, Leonard Rubin2, and Tsu-Jae King Liu1 1Department of Electrical Engineering and Computer Sciences University of California, Berkeley, 2Axcelis Technologies,  

Advancements in lithography have been critical to sustaining Moore's Law over the past 50+ years. As the minimum feature size of an integrated circuit (IC) has been scaled down well below the wavelength of ultraviolet light used in the photolithographic process, the semiconductor industry has faced a growing challenge of increasing transistor density at ever lower cost per transistor [1]. To pattern features with resolution and pitch beyond the limits of photolithography, more restrictive design rules [2] and "multiple-patterning" techniques have been adopted in high-volume IC manufacturing.

Self-aligned double-patterning (SADP) is a multiple-patterning approach that was first demonstrated to be advantageous for forming sub-lithographic fins in a FinFET fabrication process [3] and more generally for increasing feature density [4], which has since been used for the manufacture of non-volatile memory chips (beginning at the 34 nm node in 2008 for Micron's 32 Gb flash memory product [5]) and more recently for leading-edge microprocessors (most recently in Intel's 14 nm FinFET process [6]). It is anticipated that iterative double-patterning ("quadruple-patterning") will be needed to achieve ever higher transistor density [1]. Also, as the feature density of the lowermost interconnect layers increases, more IC layers will need to be patterned using SADP or other double-patterning techniques. As a result, patterning-related costs will escalate [7] and could bring the era of Moore's Law to an end.

To address this growing challenge, we recently proposed and demonstrated a double-patterning method that utilizes tilted ion implantation (TII) to achieve sub-lithographic features and pitches, down to below 10 nm half-pitch [8-10]. The basic concepts are to use ion implantation to alter the etch rate of a thin masking layer, and to perform the implantation at tilted angle to achieve sub-lithographic implanted regions that are self-aligned to pre-existing photoresist or hard-mask features over the masking layer on the surface of the IC layer to be patterned. The process sequences for SADP and TII double-patterning methods are compared side-by-side in Figure 1.

Figure 1. Schematic cross-sections illustrating the SADP and TII double-patterning methods. (a)-(e) are similar for both approaches: (a) the IC layer to be patterned is coated with an etch-stop layer or mask layer, e.g. SiO2; (b) a mandrel layer is then deposited. (c) photoresist is coated onto the mandrel layer; (d) photolithography is used to print features in the photoresist layer; (e) an etch process is used to transfer the photoresist pattern to the mandrel layer. Starting from (f), the process steps are different. For SADP: (f1) a relatively thin hard-mask layer is conformally deposited; (g1) an anisotropic etch process is used to form hard-mask "spacers" along the sidewalls of the mandrel features; (h1) the mandrel layer is selectively removed and the wafer is then cleaned; (i1-j1) a multi-step etch process is used to transfer the hard-mask pattern to the IC layer; (k1-l1) the spacers and the etch-stop layer are selectively removed. For TII double patterning: (f2) ion implantation is performed at positive tilt angle and also at negative tilt angle to selectively damage regions of the mask layer, leaving the central region between the mandrel features undamaged due to the shadowing effect; (g2) portions of the mask layer which are damaged are etched away more rapidly than the undamaged portions; (h2) the mandrel layer is selectively removed; (i2) an etch process is used to transfer the pattern of the mask layer to the IC layer; (j2) the mask layer is selectively removed.

This new double-patterning approach essentially inserts an ion implantation process step between lithography and etch process steps, and can be used in conjunction with SADP to achieve quadruple patterning. It should be noted that ion implantation is a relatively simple process step as compared to deposition and etch process steps, so that the TII double patterning approach is more cost-effective. Table I compares the number of steps and costs for TII double-patterning against those for SADP. Clearly the TII approach requires fewer steps, provide for more than 20 percent reduction in double-patterning cost.

 

Table I. Cost Comparison of Double Patterning Approaches

As mentioned above, the photoresist layer itself could be used as the mandrel layer in a TII double-patterning process [9], to achieve further cost savings. This is in contrast to SADP, for which the mandrel layer must be able to withstand high process temperature (greater than 150oC) associated with the hard-mask deposition process. By eliminating the deposition, etch, and clean process steps associated with the mandrel layer, the cost of TII double-patterning can be brought down to only ~50 percent of the cost of SADP.  Thus, TII double-patterning presents a technological pathway for the semiconductor industry to extend the era of Moore's Law.

References:

[1]   Mark Lapedus, "What If EUV Fails?" Semiconductor Engineering, April 17, 2014. http://semiengineering.com/what-if-euv-fails/

[2]   C. Webb, "45nm Design for Manufacturing," Intel Technology Journal, vol. 12, no. 2, pp. 121-130, 2008.

[3]   Y.-K. Choi, T.-J. King, C. Hu, "Nanoscale CMOS spacer FinFET for the terabit era," IEEE Electron Device Letters, Vol. 23, No. 1, pp. 25-27, 2002.

[4]   Y.-K. Choi, J. S. Lee, J. Zhu, G. A. Somorjai, L. P. Lee, J. Bokor "Sublithographic nanofabrication technology for nanocatalysts and DNA chips," Journal of Vacuum Science and Technology B, vol. 21, p. 2951, 2003.

[5]   Ann S. Mutschler, "Intel, Micron launch 34-nm, 32-Gb NAND flash memory at SSDs," EDN Network, May 29, 2008. http://www.edn.com/electronics-news/4326011/Intel-Micron-launch-34-nm-32-Gb-NAND-flash-memory-at-SSDs

[6]   S. Natarajan et al, "A 14nm Logic Technology Featuring 2nd-Generation FinFET Transistors, Air-Gapped Interconnects, Self-Aligned Double Patterning and a 0.0588µm2 SRAM cell size," in IEDM Tech. Dig, 2014, pp. 71"“73.

[7]   A. Raley, S. Thibaut, N. Mohanty, K. Subhadeep, S. Nakamura, A. Ko, D. O'Meara, K. Tapily, S. Consiglio, P. Biolsi "Self-aligned quadruple patterning integration using spacer on spacer pitch splitting at the resist level for sub 32nm pitch applications," Proc. SPIE vol. 9782, Advanced Etch Technology for Nanopatterning V, 97820F (April 1, 2016).

[8]   P. Zheng, S. Kim, D. Connelly, K. Kato, F. Ding, L. Rubin and T.-J. King Liu, "Sub-lithographic Patterning via Tilted Ion Implantation for Scaling beyond the 7 nm Technology Node," early access available at IEEE Transactions on Electron Devices IEEE Transactions on Electron Devices, Vol 64, No. 1, pp. 231-236, 2017 http://ieeexplore.ieee.org/document/7740901/

[9]   P. Zheng, "Advanced MOSFET Structures and Processes for Sub-7 nm CMOS Technologies"

Ph.D. dissertation, Department of Electrical Engineering and Computer Sciences, University of California at Berkeley, Berkeley, CA, USA, 2016: https://www2.eecs.berkeley.edu/Pubs/TechRpts/2016/EECS-2016-189.pdf

[10] Rick Merritt, "Process Makes Smaller, Cheaper Chips" EE Times, January 6, 2017.    http://www.eetimes.com/document.asp?doc_id=1331098

   

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