Finding The Road To Next-gen Chips
New transistor and IC technologies are rising to address the issues of complexity, cost and risk as manufacturers and researchers alike look beyond conventional CMOS device scaling evolution. Multiple manufacturers and researchers are seeking new paths and innovating new processes and materials to find lower cost, higher performing solutions for next-generation chips "“ Mark Andrews technical editor at SiS explores several leading and promising avenues for devices below 10 nm.
Some of the world's largest semiconductor manufacturers, fabless design houses, startups and materials innovators all share a common goal: create paths to next-generation device technologies that reduce complexity and cost while delivering better performance.
The search for alternatives to existing scaling roadmaps is seen as essential by growing numbers of supply chain industry experts who believe that costs and complexities have grown to the point that only the largest fabs and device makers can compete. While global fab leaders can benefit from multi-billion dollar investments tied to their unique product road maps, opportunities have grown for other technologies; researchers are constantly seeking alternatives and novel approaches that avoid IP and patent issues while offering means to create faster, secure technologies.
Micro electromechanical system (MEMS) sensors exemplify advanced technology untethered to the costs and volumes of 300mm fabs. MEMS designs do not rely on cutting edge hardware, but instead often utilize legacy 200 mm technologies including refurbished tools and well established fab techniques. Such fabs can find ample reservoirs of quality, trained operators and service experts anxious to get into a new game.
MEMS technology has amply demonstrated that a major new market does not necessarily require the latest transistor technology wedded to 300mm wafers. The MEMS market took-off with the advent of smartphones in 2007. Today, MEMS growth is pegged as much on new applications including drones and IoT network devices as it is on smartphones. MEMS high-end sensors (HES) support industrial and commercial requirements along with virtual assistants and other end use products that did not exist five years ago. The ideal wafer size for MEMS is presently 200mm, which has led to six new 200 mm wafer fabs being built in China to satisfy global capacity requirements.
Many experts see node migrations as moving horizontally or vertically toward 3D designs before large scale adoption of extreme ultraviolet (EUV) lithography that manufacturers such as Intel, Samsung and TSMC have predicted will occur later this decade. Many expect significant improvements at 7 nm compared to immediately preceding nodes, which may delay the need for 5nm devices until late in the 2020s. Manufacturers are also expected to create hybrid technologies that incorporate any number of non-traditional approaches including carbon nanowires, fully-depleted silicon on insulator (FDSOI), and different types of wafer bonding. We can expect multiple iterations of existing FinFET and other 10nm architectures before the trek to 7/5 nm commences enmasse. Meanwhile, the researchers at CEA Leti report that their 3D stacking technology, CoolCube, has reached new performance milestones and that manufacturing partners for pilot production runs are now being sought. The CoolCube approach operates at lower temperatures compared to other bonding techniques, which better preserves transistor functionality during alignment and other processing steps. CoolCube attained offset pitches of 1nm or less in earlier production stages, alignment accuracy that alludes some higher temperature processes.
The drive to find new approaches to device evolution and scaling is also a product of the growing disparity between design and manufacturing capabilities. Traditional node scaling has become so expensive that it is no longer the "˜go-to' solution for increasing density and performance. To paraphrase the old analogy: if you build it, will the market buy it?
Even the largest companies explore alternatives. This is especially true for fabless design groups that cannot sink billions into each new node since there are not always multimillion device market opportunities to amortize 10-figure investments. While fabless designers explore alternatives, major consumer device manufacturers such as Samsung and Apple are having a go at building their own mobile device chips and major data center operators including Amazon, Facebook and Google are creating cloud chip designs. This shift equates to fewer high-volume markets for independent developers and fewer instances in which high cost designs and fab expenses can be amortized across multi-tier/multi-generational product lifetimes.
Most manufacturers and supply chain vendors wish there was a pipeline full of new end use products like smartphones and laptops just waiting for top-dollar chips in multimillion quantities. There are instead new opportunities requiring a few million devices, or hundreds of thousands of chips to support automotive, Internet of Things (IoT), machine learning, augmented / virtual reality, medical device, wearable and printed flexible circuit applications. Even exciting new markets such as the IoT that is already generating billions in revenue seek low-cost chips, with more than one major potential user of IoT technology seeking advanced devices at less than $1 per chip. Although seemingly "˜chump change' compared to high price legacy processors, emerging applications including the IoT/IIoT are already driving markets and moved semiconductors to 20 percent growth in 2017.
Once final figures are tallied, it's expected 2017 sales topped (USD) $400 billion while fab tool sales jumped well beyond $50 billion, both first time milestones. 2017's growth was uncommon, but the fact that so much ground was gained by emerging applications has prompted market analysts to predict solid opportunities in 2018 and beyond. The SEMI trade group estimates automotive electronics markets (ADAS, vehicle autonomy, infotainment, etc.) will achieve (USD) $280 billion in sales by 2020 and that electronic medical devices will grow to more than $200 million by 2024. Today's $2 trillion supply chain is projected to reach $4 trillion by 2022. Now that's potential.
The appetite for alternative technologies is driven by more than cost and complexity avoidance. There is a growing realization that it is simply harder to design, inspect and test devices at advanced nodes compared to 28 nm transistors in classic 2D architectures. Physical effects that impact device performance and product lifetime are more fully understood now since industry has tried its hands at next generation ICs. As geometries shrink and die are made from thinned wafers, so also do heat buildup, ESD and signal interference become more critical issues; this often results in more elaborate (and expensive) testing protocols and mitigation techniques. Smaller die also frequently have different current requirements to speed signals across increasingly complex circuit pathways, and even if this is an incremental increase in the microwatt range, it represents still another hurdle that designers and manufacturers must overcome.
These factors are of particular concern in the ever-increasing number of mobile applications. An excellent example of new challenges can be found in lithographic edge placement errors (EPEs) that were manageable at larger nodes, but are increasingly counterproductive as geometries shrink to 7/5nm and below. EUV by itself won't solve all the issues related to reduced node and transistor feature scaling. Defect elimination also becomes more challenging at the parts-per-trillion scale, which effects multiple critical resources across the supply chain from liquid and gaseous chemicals to filtration, sub-fab vacuum and abatement, and so forth. There is no such thing as a perfectly smooth line at atomic scale and variations that were inconsequential at larger nodes can be "˜killer' below 10 nm.
The issues large and small related to device scaling, increasing performance and reducing power consumption are finding solutions through a diverse array of new tools and materials innovations. In addition, new processes and techniques that improve upon throughput and accuracy of existing techniques are showing promise, not just for emerging markets but also for reducing costs and allowing for more product variation in the multimillion device markets with us today
Applied Materials, a longtime, industry-leading supplier of materials innovation, is one company that is looking ahead to next-generation needs while it supports current requirements in global high volume manufacturing centers.
At the 2017 SPIE Advanced Lithography conference, Applied Materials' Uday Mitra, vice president of etch and patterning strategy, coauthored a paper about reducing edge placement errors that reported they had cut the critical line error rate (LRE) from a standard 3.4 nm to 1.3 nm through the use of the company's Sym3 reactor and proprietary techniques. Performance gains can also be achieved through the use of the latest, highly advanced 3D modeling programs such as Coventor's software solutions that enable designers to perform process integration experiments in virtual space. This data also provides a means to estimate yield losses in pattern transfer due to variations in side wall profiles and LER.
Semiconductor supply chain leaders are also addressing the needs of present and future designers and manufacturers through expansion, diversification and comprehensive services targeting the needs of a more diverse international manufacturing community. AP&S International GmbH (Donaueschingen, Germany) is a prime example of a company that has reinvented itself, expanded and then redesigned its offerings to meet the needs of global manufacturers. The company specializes in different aspects of wet processing and offers a unique metal lift-off approach to support 3D device manufacturing as well as solutions for both front- and back-end production chains.
To support large companies, research groups and startups"”all with unique requirements, the company offers a wide range of tools beginning with manual wet benches through fully automated, multi-chamber systems as both new and refurbished tools. Recognizing that smaller customers often need more assistance incorporating new tools into their operations, the company offers extensive pre-sales and after-sales support, including a fully functioning Demo Center where customers can literally try-it-before-they-buy-it. Support now includes a growing array of IoT interfaces paired with 24/7 off-site customer support that is accessible by technicians whenever needed. At SEMICON Europa (November 2017) the company introduced its augmented reality programs for diagnosis and trouble-shooting. These additional capabilities and a customer service mentality that permeates all they offer is especially beneficial for remedying a wide variety of issues that may arise over the course of production cycles. AP&S also reconditions equipment (their own and other major brands,) which helps startups and research institutes leverage limited capital equipment budgets.
Newer, smaller semiconductors are frequently being designed to utilize ultra-thinned wafers, which present their own unique handling and testing requirements. Defects occurring throughout production, especially during the grinding and polishing (CMP process stages), may crack delicate die or set the stage for eventual device failures.
UnitySC (Grenoble, France) is expanding thanks in part to the popularity of its 4See Series of devices that go beyond traditional backside wafer inspection. Designed to spot nanometer-scale defects, their approach utilizes phase-shift deflectometry (PSD) and conformal confocal (CC) inspection technology; Unity's system is unique and patented. A number of customers are utilizing the UnitySC system for inspection of two-layer, bipolar IGBT power devices. The company expects greater growth potential as spotting more defects on the backside of a semiconductor as well as its top with one tool becomes more critical with each new device generation.
Another sign of expanding reliance on sophisticated inspection and metrology tools was an announcement by Rudolph Technologies in 2017 that its Firefly inspection system was selling briskly in China and that the first delivered devices had qualified to enter production. Firefly provides high-resolution visual and non-visual inspection to support a variety of advanced packaging processes including fan-out wafer-level packaging, panel- and wafer-level CSP. Rudolph expected over (USD) $5 million in revenue in Q3 2017 from the systems.