Adesto and Cadence collaborate for emerging IoT devices
Adesto Technologies and Cadence Design Systems have announced they have collaborated to expand the ecosystem around the Expanded Serial Peripheral Interface (xSPI) communication protocol to enable higher transfer rates and lower latency for flash memory in internet of things (IoT) devices. The Cadence Memory Model for xSPI is the first commercially available model that allows customers to ensure optimal use of the octal NOR flash with the host processor in an xSPI system, including support for Adesto’s EcoXiP octal xSPI non-volatile memory (NVM).
Flash memory devices in IoT systems require increasingly higher transfer rates and lower latency, especially as these products now frequently run code-intensive wireless stacks and support local artificial intelligence (AI) processing. Expanding the flash SPI accesses from the traditional four I/Os (quad SPI) to eight I/Os (octal SPI) with the xSPI serial synchronous protocol increases the serial NOR flash throughput and provides a more efficient solution for emerging applications.
“Support for new protocols, such as xSPI, is critical for standard adoption and will help enable a new class of IoT devices,” said David Peña, verification IP product management director, System & Verification Group at Cadence. “Cadence worked closely with Adesto and other JEDEC members to drive development of the xSPI standard, and we’ve broadened our collaboration to facilitate ecosystem development. The availability of the memory model for Adesto’s EcoXiP and host controller design IP for xSPI devices enables joint customers to quickly and easily adopt xSPI while developing their products.”
One of the first NOR flash devices to support xSPI, Adesto’s EcoXiP NVM eliminates the need for expensive on-chip embedded flash in a broad range of emerging IoT applications. It hits the sweet spot for power, system cost and performance, with significantly lower power consumption compared to other octal devices and offers dramatically higher performance versus quad SPI devices.
“Moving intelligence to the edge can provide significant advantages, but heavier local processing means that architects must revisit their system’s memory architecture,” said Gideon Intrater, Adesto’s CTO. “xSPI makes it easier for system designers to reap the benefits of octal devices like EcoXiP for smarter, more efficient and user-friendly designs. The new Cadence memory model will help our EcoXiP customers to have even more optimized systems.”
The Cadence memory model for xSPI is part of the Cadence Verification Suite and is optimized for Xcelium Parallel Logic Simulation, along with supported third-party simulators. The suite is comprised of best-in-class core engines and verification fabric technologies that support the Cadence Intelligent System Design™strategy, enabling SoC design excellence.
