SEMICON West to focus on EUV, 450mm & 3D transistors
The critical processes and technologies necessary to continue Moore's Law are currently more uncertain than ever.
The latest information on EUV lithography, 3D transistors, 450mm wafer processing, and other challenges to preserving the pace of Moore's Law, leading authorities will provide their insights, perspectives and predictions at SEMICON West.
The conference will be held between July 9th and 11th in San Francisco, California.
Although progress to take EUV lithography into the realm of high-volume manufacturing continues to be made, the readiness of source technologies, mask infrastructure and resist performance are still not known with a high degree of certainty.
Until EUV lithography is ready for high-volume manufacturing, the industry will continue to rely on double-patterning and even multiple-patterning lithography schemes using 193 immersion technology to take it beyond 22nm.
How the industry will address these barriers, uncertainties and alternatives will be the focus of the lithography session at SEMICON West.
The sessions will include the following speakers and topics:
Skip Miller, ASML - NXE Platform Performance and Volume Introduction
Stefan Wurm, SEMATECH - Mask and Resist Infrastructure Gaps
Ben Rathsack, Tokyo Electron - Advances in Directed Self-Assembly Integration and Manufacturability on 300mm Wafers
Mike Rieger, Synopsys - Collaboration to Deliver Lithography Solutions
Nikon Precision - ArF Lithography Extension Through Advanced Overlay and Imaging Solutions
The mobile market is driving the move to novel transistor architectures that offer greater performance and power benefits than traditional planar architectures.
Memory and logic manufacturers are pursuing different strategies including leveraging innovations in design rules, new channel materials and processes (e.g., MOCVD) and inspection and metrology challenges. Speakers and topics on the challenges of nonplanar transistor processing include:
Gary Patton, IBM Semiconductor Research and Development Centre - Meeting the Challenges of Next-Generation Scaling
Subramani Kengeri, GLOBALFOUNDRIES - Enabling SoC Level Differentiation Through Advanced Technology R&D
Michel Haond, STMicroelectronics - Main Features and Benefits of 14nm Ultra Thin Body and BOX (UTBB) Fully Depleted SOI (FD-SOI) Technology
Paul Kirsch, SEMATECH - Non-Silicon R&D Challenges and Opportunities
Adam Brand, Applied Materials - Precision Materials to Meet FinFET Scaling Challenges Beyond 14nm
Joe Sawicki, Mentor Graphics - New Approaches to Improving Quality and Accelerating Yield Ramp for FinFET Technology
While materials, architecture and processing technologies are undergoing revolutionary changes, wafer processing platforms are also being radically transformed with a planned transition to 450mm wafers.
For chip manufacturers and suppliers, this will involve increased levels of collaboration, further advancements in tool prototypes, and increased visibility into related supply chain implications.
The SEMICON West 450 Transition Forum will provide the latest updates on the status of 450 R&D, as well as a review of key technology considerations and a discussion of implications and opportunities for the supply chain.
Each of these programs will take place in the TechXPOT conference sessions on the exhibit floor. Other TechXPOT programs include sessions on 2.5D and 3D IC Packaging, Productivity Innovation at Existing 200mm/300mm Fabs, Silicon Photonics, Lab-to-Fab Solutions, MEMS, LED Manufacturing, and Printed and Flexible Electronics.
