EUV masks/resists go dark! A sub-20nm transistor update
In advance of the 2013 SEMICON West TechXPOTs on lithography and nonplanar transistors beyond 20nm, SEMI asked some of the speakers to comment on the challenges they wanted to highlight.
This year's SEMICON West is taking place between July 9th and 11th and will discuss front-end processing TechXPOTs on lithography (www.semiconwest.org/node/8471) and transistors below 20nm.
Updates on how technologists are meeting the critical issues associated with each of these areas will be accessible via www.semiconwest.org/node/8481. This article takes a look at the challenges with commentary from TechXPOT speakers.
EUV Lithography: Entering Competitive Advantage Phase
The outlook for EUV Lithography source readiness was a bit murky late last year as a review of the presentations at the 2012 International Workshop on EUV and Soft X-Ray Sources suggested. The workshop took place in Dublin, Ireland between 8th and 11th October 2012.
As reported by ASML at that conference, both LPP and LDP, also known as DPP, source technologies were still trying to achieve 50W of power at a high duty cycle. There was even mention of a nonconventional way to achieve scaling using a free electron laser (FEL).
Given that ASML is working to acquire Cymer (which is developing the LPP source), it probably speaks volumes about which source technology has garnered the most interest on the part of ASML.
Springtime came early to the industry, however. ASML reported at the SPIE Advanced Lithography Conference between 24th and 28th February 2013, in San Jose, California, that 55W had been demonstrated at a 100 percent duty cycle, as shown in Figures 1 and 2 below.
Figure 1. Mask-oscillator power amplifier (MOPA) PrePulse technology validated with power, dose stability, and collector protection. SOURCES: ASML/Cymer (David Brandt)
Figure 2. 55W EUV power demonstrated using mask-oscillator power amplifier (MOPA) PrePulse showing good dose control and under collector protection conditions. SOURCES: ASML/Cymer (David Brandt)
What's more, results were shown for 9nm hp imaging - the first time a single-digit result from a single exposure had been achieved, as illustrated in Figure 3 below.
Figure 3. Demonstrated 9nm hp L/S pattern with EUV single SADP flow. SOURCES: ASML, imec, Applied Materials (2/13)
Stefan Wurm, director of Lithography at SEMATECH, told SEMI he was very encouraged by the results reported at SPIE. "They've demonstrated significant improvement and if they can demonstrate significant improvement at the next milestone (i.e., June-July timeframe), then tools will ship with the source productivity (i.e., 50-60wph) that IC manufacturers expect for a pilot line," noted Wurm.
Once the next source milestone is achieved, Wurm believes the industry will shift its focus to the mask side, where there is still work to be done on defects. "Nobody has really ever used an EUV mask under high-volume manufacturing (HVM) conditions, so you have to think about things like mask lifetime, use cycles, cleaning frequencies - backside and frontside - and so on," said Wurm.
But don't expect to see a lot of reporting on these activities.
Wurm explained that the learning the IC manufacturers are doing with respect to masks - and resists - is now seen as giving them a competitive advantage. An outsider attending an EUV conference won't see much visibility with respect to progress.
"People might show a few nice pictures, but exactly how they do it, what they do, and what it takes to get there - they're not going to share that anymore," Wurm points out.
So as the industry begins the ramp up to SEMICON West, it finds itself poised to enter the realm of EUV pilot line production which is indeed good news. But the industry is also at the point where EUV infrastructure learning is maturing and becoming a competitive advantage.
In the meantime, lithographers are working to extend optical lithography with multiple patterning and chip design approaches, an engineering effort that Wurm says the industry is perfectly capable of doing.
Searching for New Channel Materials
Whether an IC manufacturer chooses to make the giant leap to 3D transistors (e.g., the Tri-gate), or takes an evolutionary approach (e.g., using SOI-based technology as a bridge), all roads lead to the implementation of 3D transistor architectures.
No matter what path, however, new channel materials will have to be developed. Paul Kirsch, director of the Front-end Process Division at SEMATECH, anticipates that there will be a progressive range of germanium being added to silicon - from perhaps 25 percent germanium up to 100 percent germanium - to form channels in pMOS FETs first, followed by nMOS FETs for logic applications.
"Industry has a great deal of experience with SiGe already," noted Kirsch. "It's understood how to handle that material in the fab and it's had good performance benefits in the pMOS FET." What does need more attention, however, is making SiGe work for the nMOS FET - particularly for contacts and gates. Kirsch anticipates seeing SiGe entering the roadmap between the 14nm, 10nm, and 7nm nodes, with the possibility that some IC manufacturers may be able to start even sooner than 14nm.
14nm FD-SOI
STMicroelectronics is in the evolutionary camp with respect to transistor scaling. "We have opted for the planar solution (for 14nm) built on a thin silicon film above a thin buried oxide layer, which is simpler to manufacture while still offering the same fully-depleted benefits," explained Giorgio Cesana, marketing director, Technology R&D, Digital Sector, at STMicroelectronics.
With the company's 28nm FD-SOI node in production, it is now focusing on the development of the next node. "At 14nm, this will implement a set of new features for further increasing performances while optimising power consumption and operating at reduced voltage levels."
The 14nm FD-SOI node will also benefit from gate-first integration according to Cesana. "Traditionally, gate-first pFET performance is weaker than competing gate-last approaches that are better able to lower pMOS threshold voltage," he observed. "To overcome this limitation, the gate stack is built using a "flow C" integration scheme that creates fewer constraints vs. the gate-etch patterning used in the 28nm FD-SOI "flow B."
Cesana further explained that another important feature of 14nm FD-SOI will be the introduction of insitu doped SiGe:B on the pFET, combined with a <110> oriented-substrate, as a key performance booster. "On an nFET, an insitu doped SiC:P is introduced to avoid a performance penalty. Still, the 14nm node will support a dual source-drain integration scheme."
A SiGe channel obtained by germanium condensation is mandatory on the pFET side for lowering the device threshold voltage and STMicroelectronics will be adjusting the germanium concentration to match the suitable Vt value.
Learn more about lithography and nonplanar transistors beyond 20nm at SEMICON West 2013 (www.semiconwest.org). Hear from the experts - live! Registration includes free access to the exhibition hall plus all TechXPOT sessions, keynotes and executive panels.
Register for SEMICON West here (free through May 10th): www.semiconwest.org/register. For information on exhibiting, visit www.semiconwest.org/Exhibitors/ExhibitNow.
