News Article
Imec and partners' new process could increase mobility beyond 10nm MOS devices
Tensile-strained germanium tin (GeSn) MOSFET devices on silicon have been developed using solid phase epitaxy
KULeuven, imec and AIST have developed a solid phase epitaxy process to integrate germanium tin (GeSn) metal-oxide semiconductor field-effect transistor (MOSFET) devices on silicon.
For the first time, operation of depletion-mode junctionless GeSn pMOSFET on silicon was demonstrated, an important step toward achieving tensile strain in MOSFET devices, and increasing their mobility.
To improve performance in next-generation scaled complementary metal-oxide semiconductor (CMOS) devices, researchers are exploring the integration of novel materials with superior electron mobility.
This includes GeSn, a promising semiconductor candidate as channel material, due to its superior physical properties.
GeSn enables increased switching speed of MOSFET devices and can be used in fast optical communication. While most prototype GeSn channel MOSFETs are fabricated on germanium substrates, silicon integration is preferred for CMOS compatibility.
However, epitaxial growth of GeSn on silicon substrates poses several challenges, including limited solubility of tin in germanium (0.5 percent), its compositional fluctuations, tin segregation, and large lattice mismatch ( over 4 percent). Therefore, it is critical to suppress these effects to obtain high performance devices with GeSn layers.
Researchers from KULeuven, imec and AIST developed a solid phase epitaxy process, achieving ultrathin ( greater than 10nm) single-crystalline GeSn layers on silicon substrates showing tensile strain, attractive for strain engineering of germanium channels.
TEM image of NiGeSn metal S/D MOSFET. TEM is observed along [11-2], the channel direction is [-110] and the surface orientation is (111)
What's more, it reduces the difference between the direct and indirect band transition, resulting in acquisition of a direct band gap group IV material. Lastly, due to its non-equilibrium deposition conditions, the new method enables the development of GeSn with high tin concentrations .
By decreasing the channel thickness with reactive ion etching (RIE) from ~30 to ~10nm, the researchers improved the on/off ratio by more than one order of magnitude.
Also, hole depletion in the ultrathin (~10nm) GeSn layers on silicon resulted in good transfer characteristics with an on/off ratio of 84. In the future, research will focus on optimizing the GeSn MOSFET on silicon devices to further increase the channel mobility.
More details on these results will be presented at the Solid State Devices and Materials (SSDM) conference in Fukuoka, Japan on September 25th, and will be published in Applied Physics Express 2013.
