Mentor Graphics & Cadence boost TSMC's 16nm FinFET process

Mentor Graphics and Cadence Design Systems have completed enhancements to their digital tool sets for TSMC's 16nm FinFET manufacturing processes.

TSMC's 16nm Reference Flow includes new capabilities for 16nm designs in Mentor's Olympus-SoC place and route system, and the Calibre physical verification and design for manufacturing (DFM) platform.

TSMC, Mentor and Cadence completed V0.5 Design Rule Manual (DRM) and SPICE 16nm FinFET certification and will continue the certification toward V1.0.

"We've worked closely with Mentor Graphics to define new capabilities needed in the IC implementation flow to realise the benefits of 16nm FinFET technology," says Suk Lee, senior director, Design Infrastructure Marketing Division at TSMC.

"The new features build on the stable design-enabling environment that Mentor has delivered at prior nodes, which includes support for multi-patterning, low-power design, lithography checking, and design for test," he continues.

The Mentor Olympus-SoC place and route system has been enhanced to meet the TSMC 16nm design enablement and certification requirements. Innovative methodologies to support FinFET design include pattern density-aware floor planning for early metal fill density checks, MiM capacitor insertion for IR drop improvement, and support for high-resistance layer routing/optimisation enabling better quality of results.

What's more, the Calibre InRoute product allows Olympus-SoC customers to natively invoke Calibre DRC/DFM/DP signoff engines during design for more efficient and faster manufacturing closure.

16nm technology, and FinFET transistors in particular, create the need for more accurate device and interconnect parasitic extraction. To ensure the success of customer designs at 16nm, TSMC collaborated with Mentor on the Calibre xACT product enhancement via tool certification to provide high-accuracy, high-performance parasitic extraction.

The Calibre YieldEnhancer product provides new capabilities in its SmartFill facility to simplify fill rules for FinFETs, and to support a fill ECO flow, which makes it faster and easier to close a design while meeting advanced fill signoff requirements.

Mentor's Calibre RealTime integration platform adds support for automatic checking of 16nm voltage-dependent rule checks while editing layouts in Synopsys' Laker custom design environment, based on net voltages generated by SPICE simulation.

The net voltages are automatically applied to the layout during layout creation and editing to enable accurate checking. The Calibre RealTime and Synopsys Laker products leverage the OpenAccess open interface to enable a fast and smooth user experience, resulting in the best custom layout in the least amount of time.

"Every IC process node presents new challenges - that's been true since Gordon Moore formulated his famous law in the 1960s," says Joseph Sawicki, vice president and general manager of the Design-to-Silicon division at Mentor Graphics.

"But as we push closer to the limits of CMOS scaling, each node requires even more innovation and closer cooperation across the ecosystem to maintain the pace that keeps our industry healthy. Once again, Mentor and TSMC have stepped up to that challenge and delivered the needed technology right on time," explains Sawicki.

Also implemented in TSMC's 16nm FinFET reference flows are Cadence Design Systems' methodology innovations that allow customers to achieve the process benefits of higher performance, lower power consumption and smaller area.

The Cadence digital design tools were applied in a 16nm FinFET quad-core design that incorporated an ARM Cortex-A15 mobile processor for the validation of methodologies in TSMC's 16nm Reference Flow, with the goal to boost customer design power, performance and area (PPA). The flow was implemented with the Cadence Encounter Digital Implementation System and includes Cadence signoff tools: Physical Verification System, QRC Extraction, Tempus Timing Signoff Solution and Encounter Power System.

The TSMC 16nm Custom Design Reference Flow incorporates the use of optimised 16nm native SKILL process design kits (PDKs) to enable an innovative FinFET custom design flow by applying a number of fins at every design stage, together with a robust set of productivity-enhancing Virtuoso capabilities for sophisticated custom/analogue design.

New capabilities include FinFET custom placement using module generators (modgens), FinFET auto-alignment and abutment, advanced rule support for layout automation, and fluid guard ring generation. Custom/analogue tools in the flow include Cadence'sVirtuoso Schematic Editor, Virtuoso Layout Suite, Virtuoso Analog Design Environment, and Spectre Simulator. Signoff tools in the flow include QRC Extraction, Physical Verification System and Virtuoso Power System.

"As more electronics companies turn to 16nm FinFET technology for power savings and performance advantages, it's important they know their design tools and manufacturing process have been tested to ensure they work seamlessly together," comments Suk Lee. "The inclusion of these Cadence technologies in TSMC Reference Flows helps our customers meet their time-to-market goals and stay competitive in advanced technology design."

"Our early investment in FinFET technology development and our longstanding partnership with TSMC continue to create paths to the most advanced chip development in the world," concludes Chi-Ping Hsu, chief strategy officer and senior vice president of the digital and signoff group at Cadence. "We now have many customers using these flows to manufacture chips at TSMC that will soon be powering tomorrow's state-of-the-art mobile devices."