Sidense memory macros qualified for TSMC 28nm process nodes
The SHF memory IP targets advanced process node designs
Sidense Corp., a developer of non-volatile memory OTP IP cores has announced that its SHF Non-Volatile Memory (NVM) macros have met stringent JEDEC accelerated testing requirements for TSMC's 28HPM and 28HPL process nodes.
The 28nm HPM node addresses applications requiring high speed as well as low-leakage power and is suitable for many applications from networking and tablets to mobile consumer products. The 28nm HPL low-power node is best suited for cellular baseband, application processor, wireless connectivity, and programmable logic applications.
To meet JEDEC standard reliability test requirements, three lots of SHF devices at each process node underwent 1000 hours of high temperature storage (HTS) and high temperature operating life (HTOL) stress testing with no bit-cell failures.
For both process nodes, macro functionality and performance was verified across each of the FF, FS, SF, SS, and TT process corners at read and program temperatures of -40°C to +125°C. All macro configurations were successfully programmed and read in single-ended, redundant and double-redundant read modes.
"Our patented 1T-Fuse bit-cell architecture allows us to migrate Sidense 1T-OTP macros to shrinking process nodes as they become available," says Rhéal Gervais, Sidense VP of Operations. "We perform rigorous characterisation and qualification of our macros at each node and process variant, including JEDEC accelerated testing, to assure our customers that they are getting low-power non-volatile memory that is highly reliable."
The Sidense SHF One-Time-Programmable (OTP) memory subsystem is based on a patented 1T-Fuse (anti-fuse) bit-cell. The 1T-Fuse bit-cell uses gate oxide breakdown as a robust, non-reversible programming mechanism. Optimised for high-performance and a wide range of bit densities, Sidense SHF macros are available for standard CMOS processes. There are no requirements for any additional masks or processing steps.
Sidense SHF memory IP is provided as a complete, non-volatile memory (NVM) subsystem providing interfaces and features to support a range of embedded SoC applications. The SHF module integrates the OTP memory and Integrated Power Supply (IPS) hard macro blocks along with program control, programming and test interface, error correction and Built-In Self-Test (BIST) RTL. SHF applications include: code storage, ROM replacement, secure encryption key storage, configuration, fuse replacement, trimming and calibration.
