Teradyne and Test Insight to quicken IC development
The unison aims to improve software solutions and keep up with the latest needs of most advanced users in semiconductor testing
Teradyne and Test Insight have announced the release of new pattern conversion solutions for UltraFLEX to reduce design to test cycle times and expedite Silicon debug and characterisation.
The new solutions include the ability to compile hundreds of patterns in parallel using Linux-based Load Share Facilities (LSF) as well as the ability to produce binary IG-XL pattern files directly from electronic design automation (EDA) output formats.
The standalone Linux-based compiler can be integrated into users' pattern conversion flow. The compiler supports all UltraFLEX digital instruments and triggering of other UltraFLEX instrument families within a digital pattern.
The Linux compiler complements the existing Teradyne IG-XL Windows compiler for bulk conversion tasks by enabling the use of a customer's Linux based compute farm resources, which are typically used by design and DFT engineers, to generate test programs. The product has been tested and validated by several large customers and is now available for all users.
The Test Insight Tool Suite has also been updated to allow the generation of IG-XL binary pattern files directly from STIL/WGL/VCD to Teradyne UltraFLEX IG-XL binary formats within the ATEGEN toolset. It reduces the complexity of pattern conversion to a single step process by leveraging the Linux pattern compiler and the rich feature set of the Test Insight Tool Suite for pattern conversion.
Meir Gellis, CEO of Test Insigh says, "The tight cooperation with Teradyne helps us improve our software solutions and keep up with the latest needs of most advanced users in semiconductor test,
"Our customers are under increasing pressure to ramp their complex System-on-a-Chip (SOC) devices as soon as samples are available. Device data volumes typically exceed 100GB per device and these volumes have traditionally grown by 15 to 20 percent per device generation. During early ramp, test vectors can be fully regenerated 10 to 20 times, which presents test engineers with a computational bottleneck during the critical debug chip period. The Linux compiler enables our customers to compile hundreds of GBs in minutes by leveraging customers' existing compute farms. This will enable UltraFLEX customers to ramp their products faster, allowing more time to debug critical device issues," notes Gregory Smith, Vice President of SOC Marketing at Teradyne.
