Altera customers realise double core performance gain
Altera Corporation says its Stratix 10 FPGA and SoC customers are successfully achieving the anticipated double core performance gain in their designs compared to previous generation programmable devices.
Altera is working closely with several early access customers in multiple markets to benchmark their next-generation designs using Stratix 10 FPGA performance evaluation tools.
The leap in FPGA core performance customers are experiencing is a result of Intel's 14nm Tri-Gate process technology and the Stratix 10 HyperFlex architecture.
HyperFlex - Altera's next-generation core fabric architecture for Stratix 10 devices - enables FPGAs to make a significant leap in architectural innovations in over a decade and enables applications not possible using conventional FPGA architectures.
Stratix 10 FPGAs and SoCs with the HyperFlex architecture are able to meet the demands of the many advanced, performance-critical applications in the networking, communications, broadcast, military, and compute and storage markets while slashing system power.
Altera says early access customers are experiencing the significant performance gains that Stratix 10 devices deliver. Through the Stratix 10 FPGA early access program, Altera is working with several customers to run their existing designs through performance evaluation tools built for Stratix 10 FPGAs.
The customer designs target a wide range of applications and leverage a variety of hardware design approaches, including ASIC replacement designs, traditional high-performance FPGA communication designs and high-throughput data centre and computation designs. In all cases customers were said to experienceat least a 2X jump in their design's performance using Stratix 10 FPGAs.
"Altera's claim of 2X performance improvements seemed unimaginable when we first engaged in its Stratix 10 FPGA early access program," says Bernd Liebetrau, Head of CoC Digital Integration at Rohde & Schwarz. "After only a few days working together and receiving great guidance from Altera technical staff, we were able to run one of our existing designs through Altera's design tools and experience over twice the performance that our design previously ran. This level of performance will open up new applications for us that were previously unheard of in an FPGA."
In addition to benchmarking customer designs, Altera has also optimised several of its soft IP cores for the Stratix 10 HyperFlex architecture to deliver similar 2X performance gains. Altera's optical transport network (OTN) IP portfolio, running at 350 MHz in previous generation high-performance FPGAs, is achieving over 700 MHz performance with Stratix 10 devices.
Altera's 400 GbE IP, currently running with a 1024-bit wide data path in Stratix V FPGAs, operates with a 512-bit wide data path at 2X the performance with the HyperFlex architecture, delivering the same high throughput at significantly reduced area utilisation within the programmable core fabric.
Patrick Dorsey, senior director of product marketing at Altera adds, "We realise we were bold when we stated a 2X breakthrough in logic performance was achievable through architectural innovation and process technology leadership. Working side-by-side with customers, we have jointly confirmed what is possible with our next-generation Stratix 10 FPGA and SoC platform, and the results are remarkable."
About Stratix 10 FPGAs and SoCs
Stratix 10 FPGAs and SoCs are claimed to deliver 2X the core performance of previous generation high-performance devices. For high-performance systems that have strict power budgets, Stratix 10 devices allow customers to achieve up to a 70 percent reduction in power consumption compared with Stratix V FPGAs.
Stratix 10 FPGAs and SoCs also provide high levels of system integration which Altera says include:
· The highest density monolithic device with greater than four million logic elements (LEs)
· Over 10 TeraFLOPs of single-precision, hardened floating point DSP performance
· More than 4X serial transceiver bandwidth compared to previous generation FPGAs, including 28-Gbps backplane capable transceivers and a path to 56-Gbps transceivers
· A 3rd generation high-performance, quad-core 64-bit ARM Cortex-A53 processor system
· Multi-die solutions capable of integrating, SRAM, ASIC, processors and analogue components in a single package
Availability
Stratix 10 FPGA early access design software will be available for customer use in summer 2014.
