Si2 launches new protocol standard for 3D ICs
The thermal interface standard will facilitate integration into multi-vendor EDA tool flows used in the design of either 2D die or 3D-ICs
The Silicon Integration Initiative (Si2) has released a Chip Thermal Interface Protocol (CTIP) Standard for 3D Integrated Circuits (3D-IC) under the auspices of the Open3D Technical Advisory Board (TAB).
The Open3D TAB is chartered to define open standards for design data formats and interfaces to enable interoperable 2.5D and 3D design flows.
The Chip Thermal Interface Protocol (CTIP) facilitates the exchange of thermal design information required to integrate silicon die into 3D-IC stacks. This enables stack designers to simulate the thermal behaviour of the entire stack, thus ensuring that it satisfies die and stack-level requirements.
The standard does not assume that the individual die and the complete 3D-IC stack are designed by the same team or same design system, allowing maximum flexibility of die stack and package integration. The CTIP standard will facilitate integration into multi-vendor EDA tool flows used in the design of either the 2D die or the 3D-IC stacks.
Simulating thermal behaviour is critical for 3D-IC designs, as areas of high thermal load must be equally distributed throughout the entire stack of die to ensure proper operation in all expected conditions. The CTIP standard provides designers with the ability to share thermal maps and other design information, helping prevent the buildup of thermal stress points.
In the case of heterogeneous 2.5D and 3D design stacks, where chips may be sourced by multiple IP vendors and foundries, the need for communication of thermal information between vendors and customers is even more critical in order to have a viable system design.
Additional working groups for Open3D TAB members include developing standards to support:
Power Distribution Network to ensure that each stack in the die has access to the required power supply characteristics (released May 2013)
Thermal design and analysis of an entire 3D stack, including thermal constraints between neighbouring dies
Expression of design constraints into and out of the path-finding and floor planning stage of the overall design process
Stress management to ensure that no stack in the die is adversely affected by the stack level stress hot spots or thermal gradients
Physical verification to facilitate stack level physical DRC verification
Signal integrity to facilitate stack level electrical modelling
At the upcoming Design Automation Conference (DAC) in San Francisco, there will be a 3D Panel entitled, "Design for 3D: Are Standards Leading the Way or Lagging Behind? " at 3pm, on Monday, June 2nd in Room 300 at the Moscone Centre. Representatives from Qualcomm, Altera, Invensas, eda2asic, and Helic will be speaking.
Open3D TAB Members include Altera, AMD, ANSYS, Atrenta, Cadence Design Systems, Fraunhofer Institute, GlobalFoundries, Helic S.A., IBM, Intel, Invarian, Mentor Graphics, Qualcomm, R3Logic, SEMATECH, STMicroelectronics and Texas Instruments.
Si2 is one of the largest organisations of industry-leading semiconductor, systems, EDA and manufacturing companies focused on the development and adoption of standards to improve the way integrated circuits are designed and manufactured.
Now in its 26th year, Si2 says it is uniquely positioned to enable timely collaboration through dedicated staff and a strong implementation focus driven by its member companies. Si2 represents over 100 companies involved in all parts of the silicon supply chain throughout the world.