Enhancing energy savings with wireless network on a chip
A new type of computer chip incorporates a tiny, low-power transceiver, on-chip antennas and communication protocols that enable wireless shortcuts
Washington State University has developed a wireless network on a computer chip that could reduce energy consumption at huge data farms by as much as 20 percent.
Researchers led by Partha Pande, a computer engineering professor in the School of Electrical Engineering and Computer Science, have filed two patents on their wireless multi-core chip design, which could also speed up data processing.
The team, which includes associate professors Deukhyoun Heo and Benjamin Belzer, has a paper on their work in the May issue of ACM Journal on Emerging Technologies in Computing Systems and is building a prototype.
Partha Pande
While portable devices have gone efficiently wireless, the data farms that provide instant availability to text messages, video downloads and more still use conventional metal wires on computer chips. These are very wasteful for relatively long-range data exchange.
With ever growing amounts of data, sustainable computing has become of increasing interest to researchers, industry leaders and the public. As much as 99 percent of the energy for huge data warehouses is lost between the power plant and a customer's iPhone, according to "Reinventing Fire," a book by Amory Lovins and the Rocky Mountain Institute. One data centre can consume enough electricity to power a medium-sized town; in 2010, there were more than 2,000 of them in the U.S., according to the New York Times.
The amount of computing that occurs every day is growing exponentially, contributing to significant cost concerns for companies and a strain on resources. Very large data centres are looking for ways to improve efficiency.
WSU researchers led the effort to establish the first refereed journal specifically about sustainable computing, and Pande serves as editor. Most processors at data centres are multicore, which means they are made up of several processing cores. One of their major performance limitations stems from the multi-hop nature of data exchange. That is, data has to move around several cores through wires, slowing down the processor and wasting energy.
Pande has been working on his idea for a network-on-a-chip technology since receiving his doctorate in 2005. The technology he developed allows for wireless links between cores, resulting in less energy loss and higher data transfer speed.
The architecture uses wireless shortcuts to communicate between distant points on the computer chip. These single-hop shortcuts bypass intermediary nodes and directly connect one node to another.
Pande's team designed a miniature cell tower system on the computer chips. Similar to the way a cell phone works, the system includes a tiny, low-power transceiver, on-chip antennas and communication protocols that enable the wireless shortcuts.
Last year, the researchers acquired state-of the-art equipment to build and test the computer chips, which are some of the smallest and most efficient in the world. The researchers can make chips as small as 28 nm. More than 4 billion tiny transistors, which make up the chips, could fit on a period-sized dot.
The researchers are also testing chips that use extremely high frequencies and can transmit data up to ten times faster than current chips. Transmitting waves at high frequencies requires small chip infrastructures.
This work has been detailed in the paper, "Dual-Level DVFS-Enabled Millimeter-Wave Wireless NoC Architectures," by Jacob Murray et al in ACM Journal on Emerging Technologies in Computing Systems, 10 (4), May 2014, Article No. 27. doi:10.1145/2600074
The group's work has been funded by the National Science Foundation and the Army Research Office.
