Hitachi and Cadence speed up 28nm design tapeout
Cadence Design Systems, a global electronic design innovator, has announced that Hitachi has taped out its latest giga-scale design using the Cadence Tempus Timing Signoff Solution.
Hitachi also utilised Tempus Timing Signoff Optimisation (TSO), resulting in a reduction of its overall closure time to just 3 weeks down from almost 2 months.
This represents a significant improvement in ECO iterations versus its previous solution. The Tempus solution's advanced capabilities were able to analyse over 50M cells flat in the design, an analysis that normally requires a hierarchical signoff flow. Hierarchical strategies were used extensively during the implementation phase; however, flat analysis was needed at signoff to ensure the best accuracy.
The Tempus solution is a tool in a new class of massively parallel timing signoff tools and capabilities, which enable customers to shrink timing signoff closure and analysis turnaround time to a minimum.
In addition to faster time-to-tapeout, designs are produced with less pessimism, area and power consumption through physically aware and path-based analysis optimisation. By combining the massively parallelised capabilities of Tempus and QRC together and leveraging native database formats, Hitachi was able to improve time-to-tapeout well beyond those of existing mixed tool flows.
"The size and complexity characteristics of our latest design required a timing solution that could handle 50M cells quickly and efficiently," says Yuko Ito, director for Design Engineering First Department, Platform Advanced Engineering Operation, Information & Telecommunication Systems Company, Hitachi, Ltd. "The Tempus solution met our turnaround time challenge while ensuring the highest level of correlation to SPICE."
In addition, Toru Hiyama, general manager for Platform Advanced Engineering Operation, Information & Telecommunication Systems Company, Hitachi, Ltd. remarks, "The Tempus Timing Signoff Solution and QRC were the right timing platform to address our signoff analysis and closure needs. With strong support from Cadence, we expect continued success in taping-out leading-edge designs at 28nm and beyond."
"We have worked very closely with Hitachi to ensure that the Tempus solution fulfills the requirements of its next generation of product design cycles," says Anirudh Devgan, senior vice president of the Digital and Signoff Group (DSG) at Cadence. "The Tempus solution is the first innovation in a platform of signoff tools that brings a scalable and complete signoff solution to our customers now and at smaller process nodes."
