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Credo enables ASSP, ASIC and SoC designers

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Credo Semiconductor has announced it has successfully taped out its popular 28G and 56G SerDes transceiver IP on TSMC's 16-nm FinFET+ (FF+) process. By successfully porting its IP to this advanced processing node, Credo enables ASSP, ASIC and SoC designers to deliver solutions that address the growing performance and bandwidth demands of next-generation 100G and 400G networks.

"We have achieved unprecedented performance levels with our silicon-proven SerDes architectures, and expect to continue this trend on 16-nm FF+," said Bill Brennan, CEO of Credo Semiconductor. "Our architecture has broken new ground in the areas of power, noise immunity and jitter performance, and has also enabled us to deliver a 56G SerDes solution using NRZ technology -- a first for the industry. These metrics are not just a testament to the robustness of our technology, but are actually enabling greater innovation in the design of next-generation networking products."

"Porting complex SerDes technology to 16-nmFF+ is no small feat, and the fact that Credo was able to do this so quickly is a significant milestone for the industry," said Richard Wawrzyniak, senior market analyst for ASIC and SoC, Semico Research. "Today's ASSPs, ASICs and SoCs often require very high-performance communications channels, and SerDes is the perfect vehicle to achieve this performance. Credo has provided the right solution to the industry at the right time."

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