News Article
Cadence Unveils Virtuoso Advanced-Node Platform for 10nm Processes
Cadence Design Systems, Inc has announced the delivery of the new Virtuoso Advanced-Node Platform that is enabled for all advanced 10nm FinFET designs. This next-generation custom design platform delivers up to 5X improvement in designer productivity and also provides initial support for emerging 7nm technologies.
To address the challenges that come with advanced-node FinFET designs, innovative capabilities in the Cadence Virtuoso Advanced-Node Platform allow designers to better manage complexity and process effects. The key capabilities include:
"¢ Multi-patterning and color-aware layout: Supports more than four multi-patterned layers for design decomposition, enabling users to be far more productive through access to a variety of coloring options
"¢ Electrically aware design (EAD): Allows designers to address parasitic and electro-migration (EM) effects during the design cycle versus waiting until designs are completed, thereby reducing design cycles times by up to 30 percent
"¢ Module generator (ModGen)-based device array flow: Provides support for in-array routing, greatly reducing design iterations and improving designer productivity by up to 25X
"¢ 10nm custom routing: Supports new design rules, greatly simplifies layout creation and minimizes coloring errors that can be pervasive when designing on the 10nm process
"¢ In-design physical verification system (iPVS): Enables layout engineers to instantaneously detect and fix errors as designs are being implemented, which can greatly reduce design rule errors while improving overall designer productivity by up to 15 percent
To address the challenges that come with advanced-node FinFET designs, innovative capabilities in the Cadence Virtuoso Advanced-Node Platform allow designers to better manage complexity and process effects. The key capabilities include:
"¢ Multi-patterning and color-aware layout: Supports more than four multi-patterned layers for design decomposition, enabling users to be far more productive through access to a variety of coloring options
"¢ Electrically aware design (EAD): Allows designers to address parasitic and electro-migration (EM) effects during the design cycle versus waiting until designs are completed, thereby reducing design cycles times by up to 30 percent
"¢ Module generator (ModGen)-based device array flow: Provides support for in-array routing, greatly reducing design iterations and improving designer productivity by up to 25X
"¢ 10nm custom routing: Supports new design rules, greatly simplifies layout creation and minimizes coloring errors that can be pervasive when designing on the 10nm process
"¢ In-design physical verification system (iPVS): Enables layout engineers to instantaneously detect and fix errors as designs are being implemented, which can greatly reduce design rule errors while improving overall designer productivity by up to 15 percent
