Info
Info
search:

< Page of 9681 >

Industry News


Friday 9th March 2018
Imec has made considerable progress towards enabling extreme ultraviolet (EUV) lithography single exposure of N5 32 nm pitch metal-2 layers and of 36 nm pitch contact holes. Greg McIntyre, Peter De Bisschop, Danilo De Simone, Frederic Lazzarino and Victor Blanco from the imec patterning team explain some of the key steps and highlight the impact on the semiconductor industry. The results have been presented in multiple papers at the 2018 SPIE Advanced Lithography Conference.
Wednesday 7th March 2018
Kaman Precision Products offers a new, non-contact proximity sensing solution for wide ranging power electronics applications. Its built-in switch output control provides easier set-up and calibration while also delivering speed and precision in a new compact form factor. By: Kevin Conlin, Kaman Precision Products
Thursday 1st March 2018
Extreme ultraviolet and 193 immersion lithography technology and Cadence digital tools used to design 3nm CPU core
Thursday 1st March 2018
Acquisition price represents a total equity value of about $8.35 billion
Tuesday 27th February 2018
Monday 26th February 2018
Image: EUV single patterning of (left) the N5 32nm metal-2 layer, (middle) 32nm pitch dense lines, and (right) 40nm hexagonal contact holes and pillars
Monday 26th February 2018
Qualcomm anticipates that its future Snapdragon 5G mobile chipsets will use Samsung’s 7nm LPP EUV process technology
Monday 26th February 2018
Pilot line for laser-thinning advanced SiC, GaN, and sapphire wafers already processing customer substrates
Monday 26th February 2018
Thursday 15th February 2018
Live demonstrations will cover applications in computing, communications, and automotive
Wednesday 14th February 2018
Special-purpose chip reduces power consumption of public-key encryption by 99.75 percent, increases speed 500-fold.
Friday 9th February 2018
Thursday 8th February 2018
Handles homogeneous and heterogeneous chip integration with high-density packaging to enhance the efficiency of chip and passive design optimization
Thursday 8th February 2018
Above a false-color, plan-view SEM image of a lateral gallium oxide field effect transistor with an optically defined gate. From near (bottom) to far (top): the source, gate, and drain electrodes. Metal is shown in yellow and orange, dark blue represents dielectric material, and lighter blue denotes the gallium oxide substrate. Credit: AFRL Sensors Directorate at WPAFB, Ohio, US