VIDEO
Imec proposes double-row CFET for the A7 technology node
Video Summary
Geert Hellings, Program Director DTCO at imec, explains the organisation’s development of a new CFET-based standard cell architecture containing two rows of CFETs with a shared signal routing wall in between. The main benefits of this double-row CFET architecture are process simplification, and significant logic and SRAM cell area reduction according to imec’s design-technology co-optimization (DTCO) study. The new architecture allows standard cell heights to be reduced from 4 to 3.5T, compared to conventional single-row CFETs.
